Designing a 3GHz, 130nm, Intel ® Pentium® 4 processor

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 130-133

  Deleganes, Daniel ^a   Douglas, Jonathan ^a   Kommandur, Badari ^a   Patyra, Marek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COPPER; INTEGRATED CIRCUIT LAYOUT; METALLIZING; PERSONAL COMPUTERS; SEMICONDUCTING SILICON; SERVERS;

COPPER INTERCONNECT; COPPER METALLIZATION; ON-CHIP SIGNAL TRANSMISSION;

MICROPROCESSOR CHIPS;

EID: 0037887527     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. Tyagi et al., "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects", 2000 IEDM Technical Digest,pp567-570
2. Hinton et al., "A 0.18-um CMOS IA-32 Processor with a 4-GHz Integer Execution Unit", JSSC, vol. 36, no. 11, 2001.
3. J.L. Miller et al., "A 16GB/s, 0.18um Cache Tile for Integrated L2 Caches from 256KB to 2MB", Proceedings, 2000 VLSI Circuits Symposia.
4. N. Kurd et al., "A Multi-gigahertz Clocking Scheme for the Pentium® 4 Microprocessor" JSSC, vol. 36, no. 11, 2001.
5. Green, P.K., "A GHz IA-32 architecture microprocessor implemented on 0.18 /spl mu/m technology with aluminum interconnect" ISSCC, 2000. pp.98-99.