CMOS device optimization for system-on-a-chip applications

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 455-458

  Imai, K ^a   Yamaguchi, K ^a   Kudo, T ^a   Kimizuka, N ^a   Onishi, H ^a   Ono, A ^a   Nakahara, Y ^a   Goto, Y ^a   Noda, K ^a   Masuoka, S ^a   Ito, S ^a   Matsui, K ^a   Ando, K ^a   Hasegawa, E ^a   Ohashi, T ^a   Oda, N ^a   Yokoyama, K ^a   Takewaki, T ^a   Sone, S ^a   Horiuchi, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COPPER; ELECTRIC CURRENTS; GATES (TRANSISTOR); LARGE SCALE SYSTEMS; OPTIMIZATION; VOLTAGE CONTROL;

SYSTEM-ON-A-CHIP APPLICATION;

CMOS INTEGRATED CIRCUITS;

EID: 0034453378     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)