Highly manufacturable 0.25 μm multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1998, Pages 150-151

  Chang, M H ^a   Ting, J K ^a   Shy, J S ^a   Chen, L ^a   Liu, C W ^a   Wu, J Y ^a   Pan, K H ^a   Hou, C S ^a   Tu, C C ^a   Chen, Y H ^a   Sue, S L ^a   Jang, S M ^a   Yang, S C ^a   Tsai, C S ^a   Chen, C H ^a  

^a Exploratory Research Division   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; OXIDES;

DUAL GATE OXIDE PROCESS; SHALLOW TRENCH ISOLATION PROCESS;

CMOS INTEGRATED CIRCUITS;

EID: 0031642549     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)