-
1
-
-
44949240474
-
-
Semiconductor Industry Association (SIA), Intl. Tech. Roadmap for Semicond. (ITRS), SEMATECH, Austin, TX, USA, 2005 Edition and 2006 Update.
-
Semiconductor Industry Association (SIA), Intl. Tech. Roadmap for Semicond. (ITRS), SEMATECH, Austin, TX, USA, 2005 Edition and 2006 Update.
-
-
-
-
2
-
-
0035860451
-
Limits on silicon nanoelectronics for Terascale integration
-
14 Sep
-
J.D. Meindl, Q. Chen, and J.A. Davis, "Limits on silicon nanoelectronics for Terascale integration," Science, vol. 293, 14 Sep. 2001, pp. 2044-2049.
-
(2001)
Science
, vol.293
, pp. 2044-2049
-
-
Meindl, J.D.1
Chen, Q.2
Davis, J.A.3
-
3
-
-
11244285388
-
A Novel Highly Reliable Low-Power Nano Architecture: When von Neumann Augments Kolmogorov
-
Galveston, TX, USA, Sep
-
V. Beiu, "A Novel Highly Reliable Low-Power Nano Architecture: When von Neumann Augments Kolmogorov," Proc. Intl. Conf. App.-specific Sys., Arch. & Processors ASAP'04, Galveston, TX, USA, Sep. 2004, pp. 167-177.
-
(2004)
Proc. Intl. Conf. App.-specific Sys., Arch. & Processors ASAP'04
, pp. 167-177
-
-
Beiu, V.1
-
4
-
-
0141837018
-
Trends and challenges in VLSI circuit reliability
-
Jul.-Aug
-
C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, vol. 23, Jul.-Aug. 2003, pp. 14-19.
-
(2003)
IEEE Micro
, vol.23
, pp. 14-19
-
-
Constantinescu, C.1
-
5
-
-
0036931372
-
Modeling the effect of technology trends on soft error rate of combinatorial logic
-
Washington, DC, USA, Jun. 23-26
-
P. Sivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on soft error rate of combinatorial logic," Proc. Intl. Conf. Dependable Sys. & Networks DSN'02, Washington, DC, USA, Jun. 23-26, 2002, pp. 389-398.
-
(2002)
Proc. Intl. Conf. Dependable Sys. & Networks DSN'02
, pp. 389-398
-
-
Sivakumar, P.1
Kistler, M.2
Keckler, S.W.3
Burger, D.4
Alvisi, L.5
-
6
-
-
0033116184
-
Single-electron devices and their applications
-
Apr
-
K.K. Likharev, "Single-electron devices and their applications," Proc. IEEE, vol. 87, Apr. 1999, pp. 606-632.
-
(1999)
Proc. IEEE
, vol.87
, pp. 606-632
-
-
Likharev, K.K.1
-
7
-
-
33646587741
-
Rational design of DNA nanoarchitectures
-
13 Mar
-
U. Feldkamp, and CM. Niemeyer, "Rational design of DNA nanoarchitectures," Angew. Chem. Intl. Ed., vol. 45,13 Mar. 2006, pp. 1856-1876.
-
(2006)
Angew. Chem. Intl. Ed
, vol.45
, pp. 1856-1876
-
-
Feldkamp, U.1
Niemeyer, C.M.2
-
8
-
-
33846491447
-
11 bits per square centimeter
-
25 Jan
-
11 bits per square centimeter," Nature, vol. 445,25 Jan. 2007, pp. 414-417.
-
(2007)
Nature
, vol.445
, pp. 414-417
-
-
Green, J.E.1
-
9
-
-
84949198419
-
Architectures for reliable computing with unreliable nanodevices
-
Maui, HI, USA, Oct
-
K. Nicolić, A, Sadek, and M. Forshaw, "Architectures for reliable computing with unreliable nanodevices," Proc. IEEE Conf. Nanotech. IEEE-NANO'01, Maui, HI, USA, Oct. 2001, pp. 254-259.
-
(2001)
Proc. IEEE Conf. Nanotech. IEEE-NANO'01
, pp. 254-259
-
-
Nicolić, K.1
Sadek, A.2
Forshaw, M.3
-
10
-
-
85010220420
-
Reliable circuits using less reliable relays
-
E. F. Moore, and C. E. Shannon, "Reliable circuits using less reliable relays," J. Franklin Inst, vol. 262, 1956, pp. 191-208.
-
(1956)
J. Franklin Inst
, vol.262
, pp. 191-208
-
-
Moore, E.F.1
Shannon, C.E.2
-
11
-
-
0003133883
-
Probabilistic logics and the synthesis of reliable organisms from unreliable components
-
C. E. Shannon, and J. McCarthy Eds, Princeton, NJ: Princeton Univ. Press
-
J. von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in C. E. Shannon, and J. McCarthy (Eds.), Automata Studies, Princeton, NJ: Princeton Univ. Press, 1956, pp. 43-98.
-
(1956)
Automata Studies
, pp. 43-98
-
-
von Neumann, J.1
-
12
-
-
33646902164
-
Accurate reliability evaluation and enhancements via probabilistic transfer matrices
-
Munich, Germany, Mar
-
S. Krishnaswamy, G.F. Viamontes, I.L. Markov, and J.P. Hayes, "Accurate reliability evaluation and enhancements via probabilistic transfer matrices," Proc. Design Autom. & Test Europe DATE'05, Munich, Germany, Mar. 2005, pp. 282-287.
-
(2005)
Proc. Design Autom. & Test Europe DATE'05
, pp. 282-287
-
-
Krishnaswamy, S.1
Viamontes, G.F.2
Markov, I.L.3
Hayes, J.P.4
-
13
-
-
84863981780
-
PRISM: Probabilistic symbolic model checker
-
Proc. Intl. Conf. Modelling Techniques and Tools for Comp. Perf. Eval. TOOLS'02, London, UK, Springer-Verlag, Apr
-
M. Kwiatkowska, G. Norman, and D. Parker, "PRISM: Probabilistic symbolic model checker," Proc. Intl. Conf. Modelling Techniques and Tools for Comp. Perf. Eval. TOOLS'02, London, UK, Springer-Verlag LNCS vol. 2324, Apr. 2002, pp. 200-204.
-
(2002)
LNCS
, vol.2324
, pp. 200-204
-
-
Kwiatkowska, M.1
Norman, G.2
Parker, D.3
-
14
-
-
84871809764
-
Description framework for proxel-based simulation of a general class of stochastic models
-
Philadelphia, USA, Jul
-
S. Lazarova-Molnar, and G. Horton, "Description framework for proxel-based simulation of a general class of stochastic models," Proc. Summer Comp. Simulation Conf. SCSC'05, Philadelphia, USA, Jul. 2005.
-
(2005)
Proc. Summer Comp. Simulation Conf. SCSC'05
-
-
Lazarova-Molnar, S.1
Horton, G.2
-
15
-
-
33744479056
-
Evaluating circuit reliability under probabilistic gate-level fault models
-
Laguna Beach, CA, USA, May
-
K. N. Patel, I. L. Markov, and J. P. Hayes, "Evaluating circuit reliability under probabilistic gate-level fault models," Proc. Intl. Workshop Logic Synthesis (IWLS'03), Laguna Beach, CA, USA, May 2003, pp. 59-64.
-
(2003)
Proc. Intl. Workshop Logic Synthesis (IWLS'03)
, pp. 59-64
-
-
Patel, K.N.1
Markov, I.L.2
Hayes, J.P.3
-
16
-
-
33646950897
-
Probability analysis of combination systems and their reliability
-
Nov-Dec
-
V. L. Levin, "Probability analysis of combination systems and their reliability," Eng. Cyber., no. 6, Nov-Dec. 1964, pp. 78-84.
-
(1964)
Eng. Cyber
, Issue.6
, pp. 78-84
-
-
Levin, V.L.1
-
17
-
-
24944533787
-
Faults, error bounds and reliability of nanoelectronic circuits
-
Jul
-
J. Han, E.R. Taylor, J.B. Gao, and J.A.B. Fortes, "Faults, error bounds and reliability of nanoelectronic circuits," Proc. Intl. Conf. Appl.-Specific Sys., Arch. & Proc. ASAP '05, Jul. 2005, pp. 247-253.
-
(2005)
Proc. Intl. Conf. Appl.-Specific Sys., Arch. & Proc. ASAP '05
, pp. 247-253
-
-
Han, J.1
Taylor, E.R.2
Gao, J.B.3
Fortes, J.A.B.4
-
18
-
-
0003448310
-
Bayesian networks and decision graphs
-
second edition, New york, USA
-
F.V. Jensen, and T.D. Nielsen, "Bayesian networks and decision graphs," Springer Verlag , second edition, New york, USA, 2007.
-
(2007)
Springer Verlag
-
-
Jensen, F.V.1
Nielsen, T.D.2
-
19
-
-
34548239420
-
-
V. Beiu, W. Ibrahim, Y. A. Alkhawwar, and M. H. Sulieman, Gate failures effectively shape multiplexing, Proc. IEEE Intl. Symp. Defect & Fault Tolerance in VLSI Sys. (DFT'06), Arlington/Washington, DC, USA, Oct. 2006, pp 29-40.
-
V. Beiu, W. Ibrahim, Y. A. Alkhawwar, and M. H. Sulieman, "Gate failures effectively shape multiplexing," Proc. IEEE Intl. Symp. Defect & Fault Tolerance in VLSI Sys. (DFT'06), Arlington/Washington, DC, USA, Oct. 2006, pp 29-40.
-
-
-
-
20
-
-
44949174940
-
-
V. Beiu, and W. Ibrahim, On computing nanoarchitectures using unreliable nano-devices, in S.E. Lyshevski (Ed.), Nano- and Molecular-Electronics Handbook, London, UK: Talylor & Francis, May 2007, Chp. 12, pp. 1-49.
-
V. Beiu, and W. Ibrahim, "On computing nanoarchitectures using unreliable nano-devices," in S.E. Lyshevski (Ed.), Nano- and Molecular-Electronics Handbook, London, UK: Talylor & Francis, May 2007, Chp. 12, pp. 1-49.
-
-
-
-
21
-
-
38049170881
-
What von Neumann did not say about multiplexing: Beyond gate failures - The gory details
-
Proc. Intl. Work-conf. Artif Neural Networks IWANN'07, San Sebastian, Spain, Jun
-
V. Beiu, W. Ibrahim, and S. Lazarova-Molnar, "What von Neumann did not say about multiplexing: Beyond gate failures - The gory details," Proc. Intl. Work-conf. Artif Neural Networks (IWANN'07), San Sebastian, Spain, Jun. 2007, Springer LNCS 4507, pp. 487-496.
-
(2007)
Springer LNCS
, vol.4507
, pp. 487-496
-
-
Beiu, V.1
Ibrahim, W.2
Lazarova-Molnar, S.3
-
22
-
-
44949241437
-
A fresh look at majority multiplexing - When devices get into the picture
-
Hong Kong, Aug
-
V. Beiu, W. Ibrahim, and S. Lazarova-Molnar, "A fresh look at majority multiplexing - When devices get into the picture," Proc. IEEE Intl. Conf. Nanotech. (IEEE-NANO '07), Kowloon, Hong Kong, Aug. 2007, pp. 883-888.
-
(2007)
Proc. IEEE Intl. Conf. Nanotech. (IEEE-NANO '07), Kowloon
, pp. 883-888
-
-
Beiu, V.1
Ibrahim, W.2
Lazarova-Molnar, S.3
-
23
-
-
38149093277
-
Serial addition: Locally connected architectures
-
Nov
-
V. Beiu, S. Aunet, J. Nyathi, R. R. Rydberg III, and W. Ibrahim, "Serial addition: Locally connected architectures," IEEE Trans. Circ. & Sys. I-Sp. Issue Nanoelectr. Circ. & Nanoarchs., Nov. 2007, vol. 84, pp. 2564-2579.
-
(2007)
IEEE Trans. Circ. & Sys. I-Sp. Issue Nanoelectr. Circ. & Nanoarchs
, vol.84
, pp. 2564-2579
-
-
Beiu, V.1
Aunet, S.2
Nyathi, J.3
Rydberg III, R.R.4
Ibrahim, W.5
-
25
-
-
34548292194
-
On the reliability of four full adder cells
-
Dubai, UAE, Nov, to be published
-
W. Ibrahim, V. Beiu, and Y. A. Alkhawwar, "On the reliability of four full adder cells," Proc. IEEE Intl. Design & Test Workshop (IDT'06), Dubai, UAE, Nov. 2006, to be published.
-
(2006)
Proc. IEEE Intl. Design & Test Workshop (IDT'06)
-
-
Ibrahim, W.1
Beiu, V.2
Alkhawwar, Y.A.3
-
26
-
-
20344369804
-
Design and analysis of SET circuits: Using MATLAB and SIMON
-
Munich, Germany, Aug
-
M. H. Sulieman, and V. Beiu, "Design and analysis of SET circuits: Using MATLAB and SIMON," Proc. IEEE Conf. Nanotech. (IEEE-NANO'O4), Munich, Germany, Aug. 2004, pp. 618-621.
-
(2004)
Proc. IEEE Conf. Nanotech. (IEEE-NANO'O4)
, pp. 618-621
-
-
Sulieman, M.H.1
Beiu, V.2
-
27
-
-
44949151062
-
Reliability Analysis of Large Circuits Using Scalable Techniques and Tools
-
Nov
-
D. Bhaduri, S.K. Shukla, P.S. Graham, and M.B. Gokhale, "Reliability Analysis of Large Circuits Using Scalable Techniques and Tools," IEEE Trans. Circ. & Sys. I, Nov. 2007, vol. 84, pp. 2447-24.
-
(2007)
IEEE Trans. Circ. & Sys. I
, vol.84
, pp. 2447-2524
-
-
Bhaduri, D.1
Shukla, S.K.2
Graham, P.S.3
Gokhale, M.B.4
-
28
-
-
0031224423
-
SIMON: A simulator for single-electron tunnel devices and circuits
-
Sep
-
C. Wasshuber, H. Kosina, and S. Selberherr, "SIMON: A simulator for single-electron tunnel devices and circuits," IEEE Trans. CAD, vol. 16, Sep. 1997, pp. 937-944.
-
(1997)
IEEE Trans. CAD
, vol.16
, pp. 937-944
-
-
Wasshuber, C.1
Kosina, H.2
Selberherr, S.3
|