Gate failures effectively shape multiplexing

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2006, Pages 29-37

  Beiu, V ^a   Ibrahim, W ^a   Alkhawwar, Y A ^a   Sulieman, M H ^a  

^a UNITED ARAB EMIRATES UNIVERSITY   (United Arab Emirates)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL GEOMETRY; GATEWAYS (COMPUTER NETWORKS); MULTIPLEXING; REDUNDANCY; RELIABILITY ANALYSIS;

GEOMETRIC VARIATIONS; MUX SCHEMES; PROBABILITY TRANSFER MATRICES; REDUNDANCY FACTOR;

CMOS INTEGRATED CIRCUITS;

EID: 34548239420     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2006.33     Document Type: Conference Paper

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