-
1
-
-
6444244340
-
A 2.4-GHz CMOS transceiver for bluetooth
-
Dec.
-
H. Darabi, et al, "A 2.4-GHz CMOS transceiver for bluetooth," IEEE J. Solid-State Circuits, Vol. 36, pp. 2016-2024, Dec. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 2016-2024
-
-
Darabi, H.1
-
3
-
-
0036564670
-
Linearity and low-noise performance of SOI MOSFETs for RF applications
-
A.O. Adam et al., "Linearity and low-noise performance of SOI MOSFETs for RF applications," IEEE Trans. Electron Devices, Vol 49, No5, pp. 881-888, 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.5
, pp. 881-888
-
-
Adam, A.O.1
-
4
-
-
0012318609
-
-
US Patent 6,348,718B1
-
D. W. R. Leipold, W. H. Schwartz, and K. H. Kraus, US Patent 6,348,718B1, "Integrated CMOS circuit for use at high frequencies,", 2002
-
(2002)
Integrated CMOS Circuit for Use at High Frequencies
-
-
Leipold, D.W.R.1
Schwartz, W.H.2
Kraus, K.H.3
-
5
-
-
0033703261
-
A scalable substrate noise coupling model for design of mixed-signal IC'S
-
June
-
A. Samvedam, A. Sadate, K. Mayaram, T. S. Fiez, "A scalable Substrate Noise Coupling Model for Design of Mixed-Signal IC'S," IEEE. Solid State Circuits, vol. 35, pp. 895-904, June, 2000.
-
(2000)
IEEE. Solid State Circuits
, vol.35
, pp. 895-904
-
-
Samvedam, A.1
Sadate, A.2
Mayaram, K.3
Fiez, T.S.4
-
6
-
-
0033875648
-
Physical modeling of spiral inductors on silicon
-
C.P. Yue and S.S. Wong, "Physical modeling of spiral inductors on silicon," IEEE Trans. on Electron Devices, Vol 47, pp. 560-568, 2000.
-
(2000)
IEEE Trans. on Electron Devices
, vol.47
, pp. 560-568
-
-
Yue, C.P.1
Wong, S.S.2
-
7
-
-
0036494552
-
Electron and hole mobility in silicon at large operation temperature-Part I: Bulk mobility
-
March
-
S. Reggiani, et al., "Electron and hole mobility in silicon at large operation temperature-Part I: Bulk mobility," IEEE. Trans. On Electron Device, Vol. 49, pp. 490-499, March 2002.
-
(2002)
IEEE. Trans. On Electron Device
, vol.49
, pp. 490-499
-
-
Reggiani, S.1
-
8
-
-
19244372853
-
Analog integration in a 0.35 μm Cu metal pitch, 0.1 μm gate length, low-power digital CMOS technology
-
A. Chatterjee, et al., " Analog integration in a 0.35 μm Cu metal pitch, 0.1 μm gate length, low-power digital CMOS technology," IEDM '01 Tech. Dig., pp. 211, 2001.
-
(2001)
IEDM '01 Tech. Dig.
, pp. 211
-
-
Chatterjee, A.1
-
9
-
-
0032272978
-
Shallow trench isolation for advanced ULSI CMOS technologies
-
M. Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder, I.-C Chen, "Shallow trench isolation for advanced ULSI CMOS technologies" IEDM '98 Tech. Dig., pp. 133-136, 1998.
-
(1998)
IEDM '98 Tech. Dig.
, pp. 133-136
-
-
Nandakumar, M.1
Chatterjee, A.2
Sridhar, S.3
Joyner, K.4
Rodder, M.5
Chen, I.-C.6
-
10
-
-
84886447975
-
A shallow trench isolation for sub-0.13 μm CMOS technologies
-
M. Nandakumar, S. et al., "A shallow trench isolation for sub-0.13 μm CMOS technologies," IEDM '97 Tech. Dig., pp. 657-660, 1997.
-
(1997)
IEDM '97 Tech. Dig.
, pp. 657-660
-
-
Nandakumar, M.S.1
-
11
-
-
0032307874
-
A bond-pad structure for reducing effects of substrate resistance on LNA performance in a silicon bipolar technology
-
J.T. Colvin, S. S. Bhatia, K. K. O "A bond-pad structure for reducing effects of substrate resistance on LNA performance in a silicon bipolar technology," IEEE BCTM 6.2 pp. 109-112, 1991.
-
(1991)
IEEE BCTM 6.2
, pp. 109-112
-
-
Colvin, J.T.1
Bhatia, S.S.2
O, K.K.3
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