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Volumn , Issue , 2003, Pages 191-194

Static leakage reduction through simultaneous threshold voltage and state assignment

Author keywords

Algorithms; Design; Performance; Reliability

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; LEAKAGE CURRENTS; OPTIMIZATION; THRESHOLD VOLTAGE; TRANSISTORS;

EID: 0042635859     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.775881     Document Type: Conference Paper
Times cited : (33)

References (8)
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    • J.Halter and F.Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," Proc. CICC, pp. 475-478, 1997.
    • (1997) Proc. CICC , pp. 475-478
    • Halter, J.1    Ajm, F.2
  • 2
    • 0032680122 scopus 로고    scopus 로고
    • Models and algorithms for bounds on leakage in CMOS circuits
    • June
    • M.C. Johnson, et al., "Models and algorithms for bounds on leakage in CMOS circuits," IEEE Trans. CAD, pp. 714-725, June 1999.
    • (1999) IEEE Trans. CAD , pp. 714-725
    • Johnson, M.C.1
  • 3
    • 0036543067 scopus 로고    scopus 로고
    • Duet: An accurate leakage estimation and optimization tool for dual vt circuits
    • April
    • S.Sirichotiyakul, et al., "Duet: an accurate leakage estimation and optimization tool for dual Vt circuits," IEEE Trans. VLSI, pp. 79-90, April 2002.
    • (2002) IEEE Trans. VLSI , pp. 79-90
    • Sirichotiyakul, S.1
  • 4
    • 0036907253 scopus 로고    scopus 로고
    • Standby power optimization via transistor sizing and dual threshold voltage assignment
    • M.Ketkar and S.Sapatnekar, "Standby power optimization via transistor sizing and dual threshold voltage assignment," Proc. ICCAD, 2002, pp. 375-378.
    • (2002) Proc. ICCAD , pp. 375-378
    • Ketkar, M.1    Sapatnekar, S.2
  • 6
    • 0029358733 scopus 로고
    • Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
    • Aug.
    • H.Kriplani, et al., "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution," IEEE Trans. CAD, pp998-1012, Aug. 1995.
    • (1995) IEEE Trans. CAD , pp. 998-1012
    • Kriplani, H.1
  • 7
    • 0002609165 scopus 로고
    • A neutral netlist of 10 combinatorial benchmark circuits
    • F. Brglez and H.Fujiwara, "A Neutral Netlist of 10 Combinatorial Benchmark Circuits", Proc. ISCAS, 1985, pp.695-698.
    • (1985) Proc. ISCAS , pp. 695-698
    • Brglez, F.1    Fujiwara, H.2
  • 8
    • 0041694500 scopus 로고    scopus 로고
    • http://www.cbl.ncsu.edu


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.