High mobility NMOSFET structure with high-κ dielectric

IEEE Electron Device Letters

Volumn 26, Issue 10, 2005, Pages 713-715

  Passlack, Matthias ^a   Droopad, Ravi ^a   Rajagopalan, Karthik ^a   Abrokwah, Jonathan ^a   Gregory, Rich ^a   Nguyen, Danh ^b  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b Lehighton Electronics Inc   (United States)

Author keywords

Charge carrier mobility; High dieleetrics; MOSFETs

Indexed keywords

CHARGE CARRIERS; ELECTRON MOBILITY; MOLECULAR BEAM EPITAXY; PERMITTIVITY; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

CHARGE CARRIER MOBILITY; HIGH MOBILITY NMOSFET;

MOSFET DEVICES;

EID: 27144499264     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.856707     Document Type: Article

References (13)

1. W. Zhu, J.-P. Han, and T. P. Ma, "Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-κ dielectrics," IIEEE Trans. Electron Devices, vol. 51, no. 1, pp. 98-105, Jan. 2004.
2. J. Jung, C. N. Chleirigh, S. Yu, O. O. Olubuyide, J. Hoyt, and D. A. Antoniadis, "Tradeoff between mobility and subthreshold characteristics in dual-channel heterostructure n- and p- MOSFETs," IEEE Electron Device Lett., vol. 25, no. 5, pp. 562-564, May 2004.
3. M. Lee and E. A. Fitzgerald, "Optimized strained Si/strained Ge dual-channel heterostructures for high-mobility P- and N-MOSFETs," in IEDM Tech. Dig., 2003, pp. 429-432.
4. J. L. Hoyt, "Enhanced mobility CMOS," in Proc. 206th ECS Meeting, PV 2004-7, pp. 15-24.
5. 2-gated NMOSFETs," IEEE Electron Device Lett., vol. 25, no. 2, pp. 89-91, Feb. 2004.
6. R. Chau, "Benchmarking nanotechnology for high-performance and low-power transistor applications," in Proc. 4th IEEE Conf. Nanotechnology, 2004, pp. 3-6.
7. T. Ashley, A. R. Barnes, L. Buckle, S. Datta, A. B. Dean, M. T. Emeny, M. Fearn, D. G. Hayes, K. P. Hilton, R. Jefferies, T. Martin, K. J. Nash, T. J. Phillips, W. H. A. Tang, P. J. Wilding, and R. Chau, "Novel InSb-based quantum well transistors for ultrahigh speed, low power logic applications," in Proc. 7th Intl. Conf. Solid-State and Integrated-Circuit Technology, 2004, pp. P2253-P2256.
8. M. Passlack, "Methodology for development of high-κ stacked gate dielectrics on III-V semiconductors," in Materials Fundamentals of Gate Dielectrics, A. A. Demkov and A. Navrotsky, Eds. Berlin, Germany: Springer-Verlag, 2005, pp. 403-467.
9. M. Hale, S. I. Yi, J. Z. Sexton, A. C. Kummel, and M. Passlack, "Scanning tunneling microscopy and spectroscopy of gallium oxide deposition and oxidation on GaAs(001)-c(2 × 8)/(2 × 4)," J. Chem., vol. 119, no. 13, pp. 6719-6728, 2003.
10. M. Passlack, J. Wang, J. Abrokwah, and Z. Yu, U.S. Patent 6 359 294, Mar. 19, 2002.
11. M. Passlack, O. Hartin, M. Ray, and N. Medendorp, U.S. Patent 2004-0 137 673, Jul. 15, 2004.
12. D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. New York: McGraw-Hill, 1975, p. 137.
13. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, p. 850.