Automatic fault localization for property checking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 6, 2008, Pages 1138-1149

  Fey, Görschwin ^a,b   Staber, Stefan ^c   Bloem, Roderick ^d   Drechsler, Rolf ^a,b  

^a IEEE

^b UNIVERSITY OF BREMEN   (Germany)

^c OneSpin Solutions   (Germany)

^d GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Debugging; Formal verification; Satisfiability checking; Sequential circuit fault diagnosis

Indexed keywords

BOOLEAN FUNCTIONS; LINEAR SYSTEMS; LOGIC CIRCUITS; SPECIFICATIONS;

AUTOMATIC FAULT LOCALIZATION; PROPERTY CHECKING;

PROGRAM DEBUGGING;

EID: 44149107621     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.923234     Document Type: Conference Paper

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