Automatic fault localization for property checking

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4383 LNCS, Issue , 2007, Pages 50-64

  Staber, Stefan ^a   Fey, Görschwin ^b   Bloem, Roderick ^a   Drechsler, Rolf ^b  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

^b UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER SIMULATION; FAILURE ANALYSIS; HEURISTIC METHODS;

FAULT LOCALIZATION; PROPERTY CHECKING;

TEMPORAL LOGIC;

EID: 38149059749     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-70889-6_4     Document Type: Conference Paper

References (29)

1. M. Abramovici, P.R. Menon, and D.T. Miller. Critical path tracing - an alternative to fault simulation. In Design Automation Conf., pages 214-220, 1983.
2. M.F. Ali, S. Safarpour, A. Veneris, M.S. Abadir, and R. Drechsler. Post-verification debugging of hierarchical designs. In Int'l Conf. on CAD, pages 871-876, 2005.
3. M.F. Ali, A. Veneris, S. Safarpour, R. Drechsler, A. Smith, and M.S.Abadir. Debugging sequential circuits using Boolean satisfiability. In Int'l Conf. on CAD, pages 204-209, 2004.
4. A. Biere, C. Artho, and V. Schuppan. Liveness checking as safety checking. Electronic Notes in Theoretical Computer Science, 66(2), July 2002. Formal Methods for Industrial Critical Systems (FMICS'02).
5. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In Fifth International Conference on Tools and Algorithms for Construction and Analysis of Systems (TACAS'99), pages 193-207, Amsterdam, The Netherlands, March 1999. LNCS 1579.
6. R. K. Brayton et al. VIS: A system for verification and synthesis. In T. Henzinger and R. Alur, editors, Eighth Conference on Computer Aided Verification (CAV'96), pages 428-432. Springer-Verlag, Rutgers University, 1996. LNCS 1102.
7. P.-Y. Chung, Y.-M. Wang, and I. N. Hajj. Diagnosis and correction of logic design errors in digital circuits. In Design Automation Conference (DAC'03), pages 503-508, 2003.
8. G. Fey and R. Drechsler. Finding good counter-examples to aid design verification. In MEMOCODE, pages 51-52, 2003.
9. G. Fey and R. Drechsler. Efficient hierarchical system debugging for property checking. In Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'05), pages 41-46, 2005.
10. A. Groce. Error explanation with distance metrics. In International Conference on Tools and Algorithms for Construction and Analysis of Systems (TACAS'04), pages 108-122, Barcelona, Spain, March-April 2004. LNCS 2988.
11. A. Groce, D. Kroening, and F. Lerda. Understanding counterexamples with explain. In R. Alur and D. Peled, editors, Sixteenth Conference on Computer Aided Verification (CAV'04), pages 453-456. Springer-Verlag, Berlin, July 2004. LNCS 3114.
12. W. Hamscher and R. Davis. Diagnosing circuits with state: An inherently underconstrained problem. In Proceedings of the Fourth National Conference on Artificial Intelligence (AAAI'84), pages 142-147, 1984.
13. S.-Y. Huang and K.-T. Cheng. Errortracer: Design error diagnosis based on fault simulation techniques. IEEE Trans. on CAD, 18(9): 1341-1352, 1999.
14. B. Jobstmann, A. Griesmayer, and R. Bloem. Program repair as a game. In K. Etessami and S. K. Rajamani, editors, 17th Conference on Computer Aided Verification (CAV'05), pages 226-238. Springer-Verlag, 2005. LNCS 3576.
15. Z. Manna and A. Pnueli. The Temporal Logic of Reactive and Concurrent Systems *Specification*;. Springer-Verlag, 1991.
16. J.P. Marques-Silva and K.A. Sakallah. GRASP: A search algorithm for prepositional satisfiability. IEEE Trans. on Comp., 48(5):506-521, 1999.
17. K. L. McMillan. Applying SAT methods in unbounded symbolic model checking. In E. Brinksma and K. G. Larsen, editors, Fourteenth Conference on Computer Aided Verification (CAV'02), pages 250-264. Springer-Verlag, Berlin, July 2002. LNCS 2404.
18. M. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Proceedings of the Design Automation Conference, pages 530-535, Las Vegas, NV, June 2001.
19. B. Peischl and F. Wotawa. Modeling state in software debugging of VHDL-RTL designs - a model based diagnosis approach. In Automated and Algorithmic Debugging (AADEBUG'03), pages 197-210, 2003.
20. A. Pnueli. The temporal logic of programs. In IEEE Symposium on Foundations of Computer Science, pages 46-57, Providence, RI, 1977.
21. R. Reiter. A theory of diagnosis from first principles. Artificial Intelligence, 32:57-95, 1987.
22. A. Smith, A. Veneris, and A. Viglas. Design diagnosis using Boolean satisfiability. In ASP Design Automation Conf, pages 218-223, 2004.
23. S. Staber, B. Jobstmann, and R. Bloem. Finding and fixing faults. In D. Borrione and W. Paul, editors, 13th Conference on Correct Hardware Design and Verification Methods (CHARME '05), pages 35-49. Springer-Verlag, 2005. LNCS 3725.
24. O. Strichman. Accelerating bounded model checking of safety properties. Formal Methods in System Design, 24(1):5-24, January 2004.
25. A. Veneris and I. N. Hajj. Design error diagnosis and correction via test vector simulation. IEEE Trans. on CAD, 18(12): 1803-1816, 1999.
26. A. Wahba and D. Borrione. Design error diagnosis in sequential circuits. In Correct Hardware Design and Verification Methods (CHARME'95), pages 171-188, 1995. LNCS 987.
27. J. Whittemore, J. Kim, and K. Sakallah. SATIRE: A new incremental satisfiability engine. In Proceedings of the Design Automation Conference, pages 542-545, Las Vegas, NV, June 2001.
28. F. Wotawa. Debugging hardware designs using a value-based model. Applied Intelligence, 16:71-92, 2002.
29. A. Zeller and R. Hildebrandt. Simplifying and isolating failure-inducing input. IEEE Transactions on Software Engineering, 28(2): 183-200, February 2002.