Physical implementation of the DSPIN network-on-chip in the FAUST architecture

Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Volumn , Issue , 2008, Pages 139-148

  Miro Panades, Ivan ^a,b   Clermidy, Fabien ^c   Vivet, Pascal ^c   Greiner, Alain ^a  

^a SORBONNE UNIVERSITÉ   (France)

^b STMICROELECTRONICS   (France)

^c CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK-ON-CHIP; SUPPORT SHARED MEMORY;

CODE DIVISION MULTIPLE ACCESS; ELECTRIC POWER UTILIZATION; PROGRAM PROCESSORS; TELECOMMUNICATION;

MICROPROCESSOR CHIPS;

EID: 44149087903     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2008.4492733     Document Type: Conference Paper

References (17)

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