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Volumn , Issue , 2007, Pages 60-72

Asynchronous on-chip communication: Explorations on the Intel®R PXA27x processor peripheral bus

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMMERCE; PROGRAMMABLE LOGIC CONTROLLERS;

EID: 84881249658     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (20)
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    • Bainbridge, J.1    Furber, S.2
  • 3
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    • Static timing analysis for interconnect of multi-frequency soc designs
    • Logic & Physical Design Task ID 1425.001, July 2006
    • P. A. Beerel. Static Timing Analysis for Interconnect of Multi-Frequency SoC Designs. Semiconductor Research Corporation (http://www.src.org), Logic & Physical Design Task ID 1425.001, July 2006.
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    • Overview of Macromodules. Final Report, February, Contract SD-302 (ARPA), Computer Systems Laboratory, Washington University St. Louis, Missouri. NOTE: The Macromodule reports are available via URL
    • W. A. Clark, C. E. Molnar, et al. Macromodular Computer Design, Part 1: Development of Macromodules, Volume 1: Overview of Macromodules. Final Report, February 1974, Contract SD-302 (ARPA), Computer Systems Laboratory, Washington University St. Louis, Missouri. NOTE: The Macromodule reports are available via URL http://research.sun.com/async/Publications/Macromodular.html.
    • Macromodular Computer Design, Part 1: Development of Macromodules , vol.1
    • Clark, W.A.1    Molnar, C.E.2
  • 8
    • 0029191713 scopus 로고
    • Asynchronous design methodologies: An overview
    • January
    • S. Hauck. Asynchronous Design Methodologies: An Overview. Proceedings of the IEEE, 83(1):69-93, January 1995.
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    • Hauck, S.1
  • 9
    • 85172437577 scopus 로고    scopus 로고
    • Intel Corporation. IntelR PXA27x Processor Family Developer's Manual, January.Order Nr 280000-003. Download via URL,NOTE: This is the publicly available version for internal Intel Document Nrs 10397-10398 (Vol I-II), Revision 1.2 of the Bulverde EAS (External Architecture Specification), by Nigel Paver, August 2001, that we used for this exploration
    • Intel Corporation. IntelR PXA27x Processor Family Developer's Manual, January 2006, Order Nr 280000-003. Download via URL http://www.intel.com/ products/wireless/index.htm. NOTE: This is the publicly available version for internal Intel Document Nrs 10397-10398 (Vol I-II), Revision 1.2 of the Bulverde EAS (External Architecture Specification), by Nigel Paver, August 2001, that we used for this exploration.
    • (2006)
  • 11
    • 0001337809 scopus 로고
    • The limitations to delay-insensitivity in asynchronous circuits
    • W.J. Dally (Ed). NOTE: available as Caltech Report Nr CS-TR-90-02
    • A. J. Martin. The Limitations to Delay-Insensitivity in Asynchronous Circuits. Sixth MIT Conference on Advanced Research in VLSI,W.J. Dally (Ed.), pages 263-278, 1990. NOTE: available as Caltech Report Nr CS-TR-90-02.
    • (1990) Sixth MIT Conference on Advanced Research in VLSI , pp. 263-278
    • Martin, A.J.1
  • 13
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    • Intel/slistix peripheral bus test plan, revision 0.4c
    • 16 August
    • M. Schuelein. Intel/Slistix Peripheral Bus Test Plan, Revision 0.4c. Intel Internal document, 16 August 2004.
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    • Intel launches Bulverde, Marathon. The Register, URL, Monday, April 12
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    • Relative timing for interconnect of multi-frequency soc designs
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    • Traylor, R.1    Dunning, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.