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Volumn 51, Issue 7, 2004, Pages 1122-1128

A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; CHANNEL DOPING; CMOS SCALING; SHORT CHANNEL EFFECTS;

EID: 4344618116     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.829872     Document Type: Article
Times cited : (18)

References (19)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.