-
1
-
-
84906837868
-
CMOS technology for RF application
-
H. Iwai, "CMOS technology for RF application," in Proc. Int. Conf. Microelectronics, 2000, pp. 27-34.
-
(2000)
Proc. Int. Conf. Microelectronics
, pp. 27-34
-
-
Iwai, H.1
-
2
-
-
0033349875
-
Comparison between fully and partially depleted SOI MOSFETs for low-power radio-frequency applications
-
O. Rozeau, J. Jomaah, J. Boussey, C. Raynaud, J. L. Pelloie, and F. Balestra, "Comparison between fully and partially depleted SOI MOSFETs for low-power radio-frequency applications," in Proc. IEEE Int. SOI Conf., 1999, pp. 22-23.
-
(1999)
Proc. IEEE Int. SOI Conf.
, pp. 22-23
-
-
Rozeau, O.1
Jomaah, J.2
Boussey, J.3
Raynaud, C.4
Pelloie, J.L.5
Balestra, F.6
-
3
-
-
0033325117
-
Device issues in the integration of analog/RF functions in deep submicron digital CMOS
-
K. Bult, "Device issues in the integration of analog/RF functions in deep submicron digital CMOS," in IEDM Tech. Dig., 1999, pp. 423-426.
-
(1999)
IEDM Tech. Dig.
, pp. 423-426
-
-
Bult, K.1
-
4
-
-
0033100397
-
CMOS technology characterization for analog and RF design
-
Mar
-
B. Razavi, "CMOS technology characterization for analog and RF design," IEEE J. Solid-State Circuits, vol. 34, pp. 268-276, Mar. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 268-276
-
-
Razavi, B.1
-
5
-
-
0031270521
-
A SOI-RF-CMOS technology on high resistivity SIMOX substrates for microwave applications to 5 GHz
-
Nov
-
D. Eggert, P. Huebler, A. Huerrich, H. Kueck, W. Budde, and M. Vorwerk, "A SOI-RF-CMOS technology on high resistivity SIMOX substrates for microwave applications to 5 GHz," IEEE Trans. Electron Devices, vol. 44, pp. 1981-1989, Nov. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, pp. 1981-1989
-
-
Eggert, D.1
Huebler, P.2
Huerrich, A.3
Kueck, H.4
Budde, W.5
Vorwerk, M.6
-
6
-
-
0033169525
-
AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFETs
-
Aug
-
Y.-C. Tseng, W. M. Huang, D. J. Monk, P. Welch, J. M. Ford, and J. C. S. Woo, "AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFETs," IEEE Trans. Electron Devices, vol. 46, pp. 1685-1692, Aug. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 1685-1692
-
-
Tseng, Y.-C.1
Huang, W.M.2
Monk, D.J.3
Welch, P.4
Ford, J.M.5
Woo, J.C.S.6
-
8
-
-
0036456565
-
Extremely scaled fully depleted SOI CMOS
-
J. G. Fossum, V. P. Trivedi, and K. Wu, "Extremely scaled fully depleted SOI CMOS," in Proc. Int. SOI Conf., 2002, pp. 135-136.
-
(2002)
Proc. Int. SOI Conf.
, pp. 135-136
-
-
Fossum, J.G.1
Trivedi, V.P.2
Wu, K.3
-
9
-
-
0031383716
-
Design criteria for a fully depleted-0.1 mm SOI technology
-
J. A. Burns, R. S. Frankel, A. M. Soares, and P. W. Wyatt, "Design criteria for a fully depleted-0.1 mm SOI technology," in Proc. Int. SOI Conf., 1997, pp. 78-79.
-
(1997)
Proc. Int. SOI Conf.
, pp. 78-79
-
-
Burns, J.A.1
Frankel, R.S.2
Soares, A.M.3
Wyatt, P.W.4
-
10
-
-
4344581785
-
-
Silvaco International, Santa Clara, CA
-
Silvaco International, Silvaco Simulation Tools, Santa Clara, CA.
-
Silvaco Simulation Tools
-
-
-
11
-
-
0036773157
-
Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS
-
Oct
-
S. D. Kim, C. M. Park, and J. C. S. Woo, "Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS," IEEE Trans. Electron Devices, vol. 49, pp. 1748-1754, Oct. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 1748-1754
-
-
Kim, S.D.1
Park, C.M.2
Woo, J.C.S.3
-
12
-
-
0031644047
-
Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides
-
Q. Xiang, G. Yeap, D. Bang, M. Song, K. Ahmed, E. Ibok, and M.-R. Lin, "Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides," in VLSI Symp. Tech. Dig., 1998, pp. 160-161.
-
(1998)
VLSI Symp. Tech. Dig.
, pp. 160-161
-
-
Xiang, Q.1
Yeap, G.2
Bang, D.3
Song, M.4
Ahmed, K.5
Ibok, E.6
Lin, M.-R.7
-
13
-
-
49749131836
-
A physical model for MOSFET output resistance
-
J. H. Huang, Z. H. Liu, M. C. Jeng, P. K. Ko, and C. Hu, "A physical model for MOSFET output resistance," in IEDM Tech. Dig., 1992, pp. 569-572.
-
(1992)
IEDM Tech. Dig.
, pp. 569-572
-
-
Huang, J.H.1
Liu, Z.H.2
Jeng, M.C.3
Ko, P.K.4
Hu, C.5
-
14
-
-
0036498428
-
Fringing fields in sub-0.1 mm fully depleted SOI MOSFETs: Optimization of the device architecture
-
Mar
-
T. Ernst, C. Tinella, C. Raynaud, and S. Cristoloveanu, "Fringing fields in sub-0.1 mm fully depleted SOI MOSFETs: optimization of the device architecture," Solid State Electron., vol. 46, no. 3, pp. 373-378, Mar. 2002.
-
(2002)
Solid State Electron.
, vol.46
, Issue.3
, pp. 373-378
-
-
Ernst, T.1
Tinella, C.2
Raynaud, C.3
Cristoloveanu, S.4
-
15
-
-
0012301123
-
Body self-bias in fully depleted and nonfully depleted SOI devices
-
K. Hui, M. Chan, F. Assaderaghi, C. Hu, and P. K. Ko, "Body self-bias in fully depleted and nonfully depleted SOI devices," in Proc. Int. SOI Conf., 1994, pp. 65-66.
-
(1994)
Proc. Int. SOI Conf.
, pp. 65-66
-
-
Hui, K.1
Chan, M.2
Assaderaghi, F.3
Hu, C.4
Ko, P.K.5
-
16
-
-
0029406130
-
Threshold voltage model for deep-submicrometer fully depleted SOI MOSFETs
-
Nov
-
S. R. Banna, P. C. H. Chan, P. K. Ko, C. T. Nguyen, and M. Chan, "Threshold voltage model for deep-submicrometer fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 42, pp. 1949-1955, Nov. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, pp. 1949-1955
-
-
Banna, S.R.1
Chan, P.C.H.2
Ko, P.K.3
Nguyen, C.T.4
Chan, M.5
-
17
-
-
0024626928
-
Analysis of conduction in fully depleted SOI MOSFETs
-
Mar
-
K. K. Young, "Analysis of conduction in fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 36, pp. 504-506, Mar. 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, pp. 504-506
-
-
Young, K.K.1
-
18
-
-
85056911965
-
Monte Carlo simulation of a 30 nm dual-gate MOSFET: How far can silicon go?
-
D. Frank, S. Laux, and M. Fischetti, "Monte Carlo simulation of a 30 nm dual-gate MOSFET: how far can silicon go?," in IEDM Tech. Dig., 1992, pp. 553-556.
-
(1992)
IEDM Tech. Dig.
, pp. 553-556
-
-
Frank, D.1
Laux, S.2
Fischetti, M.3
-
19
-
-
0033732282
-
An analytical solution to a double-gate MOSFET with undoped body
-
Apr
-
Y. Taur, "An analytical solution to a double-gate MOSFET with undoped body," IEEE Electron Device Lett., vol. 21, pp. 245-247,
-
(2000)
IEEE Electron Device Lett.
, vol.21
, pp. 245-247
-
-
Taur, Y.1
|