Evaluation on influencing factors of board-level drop reliability for chip scale packages (fine-pitch ball grid array)

IEEE Transactions on Advanced Packaging

Volumn 31, Issue 1, 2008, Pages 66-75

  Chong, Desmond Y R ^a   Che, F X ^a,b   Pang, John H L ^c   Xu, Luhua ^c   Xiong, B S ^a   Toh, H J ^d   Lim, B K ^e  

^a United Test and Assembly Center Ltd UTAC   (Singapore)

^b STMICROELECTRONICS   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e MICRON TECHNOLOGY INC   (United States)

Author keywords

Board level drop reliability; Chip scale package (CSP); Fine pitch ball grid array (FBGA) package; Lead free; Printed circuit board (PCB) surface finish; Thermal aging

Indexed keywords

BALL GRID ARRAYS; FINITE ELEMENT METHOD; INTERMETALLICS; PRINTED CIRCUIT BOARDS; SOLDERED JOINTS; STRESS-STRAIN CURVES; THERMAL AGING; THERMAL CYCLING;

BOARD-LEVEL DROP TESTING; FINE-PITCH BALL GRID ARRAY;

CHIP SCALE PACKAGES;

EID: 40549122719     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.908024     Document Type: Article

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