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Volumn , Issue , 2003, Pages 597-602

Guidelines for structural and material-system design of a highly reliable 3D die-stacked module with copper through-vias

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; COPPER; DEFECTS; FINITE ELEMENT METHOD; GOLD; INTERCONNECTION NETWORKS; PRINTED CIRCUIT DESIGN; RESINS; SILICON WAFERS; STRESS CONCENTRATION; THERMAL CYCLING; THERMAL EXPANSION;

EID: 0038012721     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (9)
  • 1
    • 0032116366 scopus 로고    scopus 로고
    • Future system-on-silicon LSI chips
    • M. Koyanagi et al., "Future System-on-Silicon LSI Chips", IEEE Micro, vol. 18, No. 4 (1998), pp. 17-22.
    • (1998) IEEE Micro , vol.18 , Issue.4 , pp. 17-22
    • Koyanagi, M.1
  • 2
    • 0032002771 scopus 로고    scopus 로고
    • A review of 3-D packaging technology
    • S.F. Al-sarawi et al., "A Review of 3-D Packaging Technology", IEEE Trans-CPMT-B, Vol. 21, No. 1 (1998), pp. 2-14.
    • (1998) IEEE Trans-CPMT-B , vol.21 , Issue.1 , pp. 2-14
    • Al-sarawi, S.F.1
  • 3
    • 0003387354 scopus 로고    scopus 로고
    • Trends of three-dimensions packaging
    • K. Hatada, "Trends of Three-Dimensions Packaging", Proc-2000 IEMT/IMC Symp., pp. 47-52.
    • Proc-2000 IEMT/IMC Symp. , pp. 47-52
    • Hatada, K.1
  • 4
    • 0003127854 scopus 로고    scopus 로고
    • 3D LSI stacking integration and wafer thinning technology
    • K. Takahashi, "3D LSI Stacking Integration and Wafer Thinning Technology", SEMI Technol. Symp. 2000 (Session-9), pp. 37-43.
    • SEMI Technol. Symp. 2000 (Session-9) , pp. 37-43
    • Takahashi, K.1
  • 6
    • 0034822219 scopus 로고    scopus 로고
    • Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered micro thin encapsulation
    • Y. Tomita et al., "Advanced Packaging Technologies on 3D Stacked LSI utilizing the Micro Interconnections and the Layered Micro thin Encapsulation", Proc. 51st Electron. Components and Technol. Conf., Orlando, FL., May, 2001, pp. 353-360.
    • Proc. 51st Electron. Components and Technol. Conf., Orlando, FL., May, 2001 , pp. 353-360
    • Tomita, Y.1
  • 8
    • 0038479863 scopus 로고    scopus 로고
    • Superfine flip-chip interconnection in 20μm-pitch utilizing reliable microthin underfill technology for 3D stacked LSI
    • M. Umemoto et al., "Superfine Flip-Chip Interconnection in 20μm-Pitch Utilizing Reliable Microthin Underfill Technology for 3D Stacked LSI", Proc. 52nd Electron. Components and Technol. Conf., San Diego, CA., May. 2002, pp. 473-479.
    • Proc. 52nd Electron. Components and Technol. Conf., San Diego, CA., May. 2002 , pp. 473-479
    • Umemoto, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.