Design and modeling challenges for 90 NM and 50 NM

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 353-360

  Gerousis, Vassilios ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION; THRESHOLD VOLTAGE;

INPUT RECEIVER MODELING; LOW LEAKAGE DEVICE; SIGNAL WAVEFORM MODELING; TEMPERATURE INVERSION MODELING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242527271     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Y. Taur, CMOS design near the limit of scaling, IBM J. Research And Development, Vol. 46, no. 2/3 March/May 2002.
2. Mohab Anis, et al, 2002 DAC - Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Gate Clustering Technique
3. S. Tyagi et al, 2000 IEDM Tech. Digest, pp. 567-570.
4. A. Chandrakasan et al, ESSCIRC 2002, Power Aware Wireless Micro-sensor Systems.
5. Design For Variability in DSM Technologies (Sani Nassif), IEEE ISQED 2000.
6. Sani Nassif, et al, Planned for ACM publication 2003, Advanced Waveform Models for the Nano-Meter Regime.