A low power, highly scalable, vertical double gate MOSFET using novel processes

65th DRC Device Research Conference

Volumn , Issue , 2007, Pages 173-174

  Cho, Hoon ^a   Kapur, Pawan ^a   Kalavade, Pranav ^b   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 39749117543     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2007.4373704     Document Type: Conference Paper

References (7)

1. Wong et al., IEDM p.427 (1997);
2. http://public.itrs.net;
3. Cho et al., Trans. Nanotech., v.5, p.554 (2006);
4. H. Cho et al., ECS v.3 p403 (2006);
5. J. Moers et al., DRC p.191 (2001);
6. M. Mori, Trans. Elec. Dev. v.30, p. 81 (1983);
7. S. Ito et al., IEDM p. 10.7.1 (2000)