Geometry dependence of poly-Si oxidation and its application to self-align, maskless process for nano-scale vertical CMOS structures

ECS Transactions

Volumn 3, Issue 2, 2006, Pages 403-414

  Cho, Hoon ^a   Kapur, Pawan ^a   Kalavade, Pranav ^b   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CRYSTAL ORIENTATION; GATES (TRANSISTOR); MOSFET DEVICES; PHOTOLITHOGRAPHY; THERMOOXIDATION;

AREA EFFECTS; CMOS GATE STACKS; CMOS STRUCTURES; VOLUME EXPANSION;

POLYSILICON;

EID: 33846952903     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2356300     Document Type: Conference Paper

References (7)

1. B. E. Deal and A. S. Crove, "General relationship for the thermal oxidation of silicon," J. Appl. Phys., vol. 36, no. 12, p. 3770 (1965)
2. D. B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat, "Two-dimensional thermal oxidation of silicon-I. Experiments," IEEE Trans. Elec. Dev., vol. ED-34, p.1008 (1987).
3. D. B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat, "Two-dimensional thermal oxidation of silicon-II. Modeling stress effect in wet oxide," IEEE Trans. Elec. Dev., vol. ED-35, p.25 (1988).
4. M. M. Denn, Process Fluid Mechanics, Englewood Cliffs, Prentice-Hall, NJ (1980).
5. 2 interface oxidation kinetics: a physical model for the influence of high substrate doping levels. I. Theory and II. Comparison with experiment," J. Electrochem. Soc., vol. 126, pp. 1516 and 1523 (1979)
6. J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling, p. 343-347, Prentice Hall, NJ (2000)
7. H. Cho, P. Kapur, P. Kalavade and K. C. Saraswat, "A novel spacer process for sub 25nm thick vertical MOS and its integration with planar MOS device," Silicon Nanoelectronics Workshop, No. 5-16 (2005).