Vertical double-gate MOSFETs

ASDAM 2004 - Conference Proceedings, 5th International Conference on Semiconductor Devices and Microsystmes

Volumn , Issue , 2004, Pages 215-218

  Moers, J ^a   Trellenkamp, St ^b   Marso, M ^a   Hart, A V D ^a   Mantl, S ^a   Luth H ^a   Kordos P ^a  

^a FORSCHUNGSZENTRUM JÜLICH   (Germany)

^b University of Koblenz Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL EFFECTS; CURRENT FLOW; PROCESS FLOW; THIN BODY DEVICES;

ELECTRIC CURRENTS; GATES (TRANSISTOR); LITHOGRAPHY; SEMICONDUCTOR DEVICES; TRANSCONDUCTANCE;

MOSFET DEVICES;

EID: 28844465190     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. http://public.itrs.net/
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4. H.-S.P. Wong, "Beyond the conventional transistor", IBM J. Res. & Dev., Vol. 46 No. 2/3, 2002, p. 133
5. H.-S. P. Wong, K. K. Chen, Y. Taur "Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25nm Thick Silicon Channel",. IEDM Technical Digest, 1997, p. 427
6. T. Schulz, W. Rösner, L. Risen, U. Langmann "50-nm vertical sidewall transistor with high channel doping concentration", IEDM Technical Digest, 2000, p. 61
7. J. Kedzierski et al., "Metal-gate FinFET and fully-depleted DOI devices using total gate silicidation", IEDM Tech. Dig., 2002, p. 247
8. st ESSDERC 2001, pp. 191
9. St. Trellenkamp, J. Moers, A. v.d. Hart, P. Kordoš, H. Lüth, "Patterning of 25-nm-wide silicon webs with an aspect ratio of 13" Microelectronic Engineering 67-68 (2003) pp 376
10. rd ESSDERC 2003, pp. 143