Vertical double-gate MOSFET based on epitaxial growth by LPCVD

European Solid-State Device Research Conference

Volumn , Issue , 2001, Pages 191-194

  Moers, J ^a   Trellenkamp, S ^a   Vescan, L ^a   Marso, M ^a   Kordos P ^a   Luth H ^a  

^a FORSCHUNGSZENTRUM JÜLICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE GATE MOSFET;

EID: 84907539013     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2001.195233     Document Type: Conference Paper

References (6)

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3. H.-S. P. Wong, K. K. Chen, Y. Taur "Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25nm Thick Silicon Channel", International Electron Device Meeting 1997. IEDM Technical Digest, pp. 427-430
4. J.-H. Lee, G. Taraschi, A. Wie, T. A. Langdo, E. A. Fitzgerald, D. A. Antoniadis "Super Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy", International Electron Device Meeting 1999. IEDM Technical Digest, pp. 71-74
5. T. Schulz, W. Rösner, L. Risch, U. Langmann "50-nm vertical sidewall transistor with high channel doping concentration", International Electron Device Meeting 2000. IEDM Technical Digest, pp. 61
6. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, C. Hu "FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20nm", IEEE Trans. El. Dev. 47 (2000) pp. 2320-2325