Fully silicided NiSi:Hf-LaAlO3/SG-GOI n-MOSFETs with high electron mobility

IEEE Electron Device Letters

Volumn 25, Issue 8, 2004, Pages 559-561

  Yu, D S ^a   Chiang, K C ^a   Cheng, C F ^a   Chin, Albert ^a   Zhu, Chunxiang ^b   Li, M F ^b   Kwong, Dim Lee ^c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRON MOBILITY; GATES (TRANSISTOR); LANTHANUM COMPOUNDS; LEAKAGE CURRENTS; NICKEL COMPOUNDS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; RAPID THERMAL ANNEALING; SEMICONDUCTING GERMANIUM; THERMODYNAMIC STABILITY; TRANSMISSION ELECTRON MICROSCOPY; VLSI CIRCUITS;

EQUIVALENT OXIDE THICKNESS; GATE DIELECTRIC; GERMANIUM ON INSULATOR;

MOSFET DEVICES;

EID: 3943060189     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.832527     Document Type: Article

References (18)

1. H. Shang, K.-L. Lee, P. Kozlowski, C. D'Emic, I. Babich, E. Sikoki, M. Ieong, H.-S. P. Wong, K. Guarini, and W. Haensch, "Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate," IEEE Electron Device Lett., vol. 25, pp. 135-137, Mar. 2004.
2. 3 gate dielectrics," in Symp. VLSI Tech. Dig., 2003, pp. 119-120.
3. 3/Ge-on-insulator MOSFETs," in IEDM Tech. Dig., 2003, pp. 319-322.
4. 2 n- and p-MOSFETs," IEEE Electron Device Lett., vol. 24, pp. 739-741, Dec. 2003.
5. 2) polysilicon: A novel approach to very low-resistive gate (∼2Ω/□) without metal CMP nor etching," in IEDM Tech. Dig., 2001, pp. 815-828.
6. Q. Xiang, J. S. Goo, J. Pan, B. Yu, S. Ahmed, J. Zhang, and M.-R. Lin, "Strained silicon NMOS with nickel-silicide metal gate," in Symp. VLSI Tech. Dig., 2003, pp. 103-104.
7. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. Philip Wong, M. Ieong, and W. Haensch, "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., 2002, pp. 247-250.
8. H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara, "Advanced gate dielectric materials for sub-100 nm CMOS," in IEDM Tech. Dig., 2002, pp. 625-628.
9. 3 gate dielectrics with equivalent oxide thickness 5-10 Å," in Symp. VLSI Tech. Dig., 2000, pp. 16-17.
10. it ," in Symp. VLSI Tech. Dig., 1999, pp. 135-136.
11. 2 and HfAlO for CMOS, thermal stability and current transport," in IEDM Tech. Dig., 2001, pp. 463-466.
12. Q. Lu, R. Lin, P. Ranade, T.-J. King, and C. Hu, "Metal gate work function adjustment for future CMOS technology," in Symp. VLSI Tech. Dig., 2001, pp. 45-46.
13. C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A sub-400°C germanium MOSFET technology with high-κ dielectric and metal gate," in IEDM Tech. Dig., 2002, pp. 437-440.
14. H. Shang, H. O. Schmidt, K. K. Chan, M. Copel, J. A. Ott, P. M. Kozlowski, S. E. Steen, S. A. Cordes, H.-S. P. Wong, E. C. Jones, and W. E. Haensch, "High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric," in IEDM Tech. Dig., 2002, pp. 441-444.
15. Y. H. Lin, Y. C. Chen, K. T. Chan, F. M. Pan, I. J. Hsieh, and A. Chin, "The strong degradation on 30 Å oxide integrity contaminated by copper," J. Electrochem. Soc., vol. 148, no. 4, pp. F73-F76, 2001.
16. R. Tsuchiya, K. Ohnish, M. Horiuchi, S. Tsujikawa, Y. Shimamoto, N. Inada, J. Yugami, F. Ootsuka, and T. Onai, "Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface," in Symp. VLSI Tech. Dig., 2002, pp. 150-151.
17. 2 nMOS and pMOSFETs," in IEDM Tech. Dig., 2003, pp. 311-314.
18. K. Uchida, J. Koga, R. Ohba, T. Numata, and S. Takagi, "Experimental evidences of quantum-mechanical effects on low-field mobility, gate channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs," IEDM Tech. Dig., pp. 633-636, 2001.