Fast-locking hybrid PLL synthesizer combining integer & fractional divisions

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 260-261

  Woo, Kyoungho ^a   Liu, Yong ^a   Ham, Donhee ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH SWITCHING; FRACTIONAL SPUR REDUCTION CIRCUITS; FREQUENCY DIVISION MODE SWITCHING; PROTOTYPE SYNTHESIZER;

BANDWIDTH; FREQUENCY DIVISION MULTIPLE ACCESS; FREQUENCY SYNTHESIZERS; INTEGER PROGRAMMING; SWITCHING;

PHASE LOCKED LOOPS;

EID: 38849121237     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342742     Document Type: Conference Paper

References (9)