A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 5, 2004, Pages 731-739

  Cho, SeongHwan ^a   Chadrakasan, Anantha P ^b  

^a Military of South Korea   (South Korea)

^b Massachusetts Institute of Technology   (United States)

Author keywords

Fractional N; Frequency modulation; Frequency shift keying; Frequency synthesizer; Low power; Phase locked loop; Sigma delta modulation; Transmitter

Indexed keywords

BANDWIDTH; DELTA SIGMA MODULATION; ENERGY EFFICIENCY; FREQUENCY SYNTHESIZERS; MODULATORS; PHASE LOCKED LOOPS; SENSOR DATA FUSION; WIRELESS TELECOMMUNICATION SYSTEMS;

FRACTIONAL-N; FREQUENCY CHANNEL SELECTION; WIRELESS MICROSENSOR NETWORKS;

FREQUENCY SHIFT KEYING;

EID: 2442607953     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.826314     Document Type: Article

References (18)

1. E. Shih et al., "Physical layer driven algorithm and protocol design for energy-efficient wireless sensor networks," in Proc. MOBICOM, 2001, pp. 272-287.
2. S.-H. Cho and A. P. Chandrakasan, "Energy efficient protocols for low duty cycle wireless microsensor networks," in Proc. IEEE ICASSP, 2001, pp. 2041-2044.
3. S. H. Cho, "Energy efficient RF communication system for wireless sensors," Ph.D. thesis, Massachusetts Inst. of Technol., Cambridge, MA, June 2002.
4. S. Willingham, M. Perrott, B. Setterberg, A. Grzegorek, and B. MCFarland, "An integrated 2.4 GHz frequency synthesizer with 5 μs settling and 2 Mbps closed loop modulation," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2000, pp. 200-201.
5. M. Perrott, T. Tewksbury, and C. G. Sodini, "A 27 mW CMOS fractional-N synthesizer using digital compensation for 2.5 Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997.
6. D. R. MCMahill and C. G. Sodini, "A 2.5 Mb/s GFSF 5.0 Mb/s 4-FSK automatically calibrated Σ-Δ frequency synthesizer," IEEE J. Solid-State Circuits, vol. 37, pp. 18-26, Jan. 2002.
7. S. Heinen et al., "A 2.7 V 2.5 GHz bipolar chipset for digital communication," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1997, pp. 306-307.
8. T. Cho et al., "A single-chip CMOS direct-conversion transceiver for 900 MHz spread-spectrum digital cordless phones," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1999, pp. 228-229.
9. H. Rategh, H. Samavati, and T. Lee, "A CMOS frequency synthesizer with an injection-locked frequency divider for a 5 GHz wireless LAN receiver," IEEE J. Solid-State Circuits, vol. 35, pp. 780-787, May 2000.
10. H. Wang, "A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 196-197.
11. B. Razavi et al., "A 13.4 GHz CMOS frequency divider," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1994, pp. 176-177.
12. J. Lee and B. Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control," IEEE J. Solid-State Circuits, vol. 35, pp. 490-502, Aug. 2000.
13. C.-Y. Yang and S.-I. Liu, "Fast-switching frequency synthesizer with a discriminator-aided phase detector," IEEE J. Solid-State Circuits, vol. 35, pp. 1445-1452, Oct. 2000.
14. W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," in Proc. IEEE Int. Symp. Circuits and Systems, 1999, pp. 545-548.
15. F. M. Gardner, Phase Lock Techniques. New York: Wiley, 1979.
16. S. H. Cho and A. P. Chandrakasan, "A 6.5 GHz CMOS FSK modulator for wireless sensor applications," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 182-185.
17. N. Filiol et al., "A 22 mW Bluetooth RF transceiver with direct RF modulation and on-chip IF filtering," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 202-203.
18. "LMX3162 Evaluation Notes and Datasheet," National Semiconductor Corporation, Apr. 1999.