A dual-band frequency synthesizer for 802.11a/b/g with fractional-spur averaging technique

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Pellerano, Stefano ^a   Levantino, Salvatore ^a   Samori, Carlo ^a   Lacaita, Andrea L ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144436749     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M. Tiebout, C. Sandner, H. Wohlmuth, N. Da Dalt, E. Thaller "A Fully Integrated 13GHz ΔΣ Fractional-N PLL in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 386-387, Feb., 2004.
2. F. Gardner "Charge-Pump Phase-Lock Loops," IEEE Trans. Comm., vol. 28, no. 11, pp. 1849-1858, Nov., 1980.
3. S. Pellerano, S. Levantino, C. Samori, A. L. Lacaita "A 13.5mW 5GHz Frequency Synthesizer with Dynamic Logic Frequency Divider," IEEE J. of Solid-State Circuits, vol. 39, no. 2, pp. 378-383, Feb., 2004.