VLSI architectures for layered decoding for irregular LDPC codes of WiMax

IEEE International Conference on Communications

Volumn , Issue , 2007, Pages 4542-4547

  Gunnam, Kiran K ^a   Choi, Gwan S ^a   Yeary, Mark B ^b   Atiquzzaman, Mohammed ^b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b University of Oklahoma   (United States)

Author keywords

Decoder architecture; IEEE 802.16e; Irregular LDPC; Layered decoding; Low density parity check (LDPC) codes; Offset min sum; On the fly computation; Turbo decoding message passing

Indexed keywords

DECODER ARCHITECTURE; LOW-DENSITY PARITY-CHECK (LDPC) CODESS; OFFSET MIN-SUMS; ON-THE-FLY COMPUTATION;

COMPUTATION THEORY; DECODING; NETWORK ARCHITECTURE; SCHEDULING; TURBO CODES; VLSI CIRCUITS;

CHANNEL CODING;

EID: 38549086489     PISSN: 05361486     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICC.2007.750     Document Type: Conference Paper

References (17)

1. D.J.C. MacKay and R.M. Neal. "Near Shannon Limit Performance of Low Density Parity Check codes" Electronics Letters, volume 32, pages 1645-1646, Aug 1996.
2. M. Mansour and N. Shanbhag, "A 640-Mb/s 2048-bit programmable LDPC decoder chip," IEEE Journal of Solid-State Circuits, vol. 41, no.3, pp. 684-698, March 2006.
3. H. Sankar and K.R. Narayanan, "Memory-efficient sum-product decoding of LDPC codes," Communications, IEEE Transactions on, vol.52, no.8pp. 1225-1230, Aug. 2004
4. Hocevar, D.E., "A reduced complexity decoder architecture via layered decoding of LDPC codes," Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on , .pp. 107-112, 13-15 Oct. 2004
5. J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier and X. Y. Hu, "Reduced-complexity decoding of LDPC codes," IEEE Trans. on Communications, vol. 53, pp. 1288-1299, Aug. 2005.
6. Blanksby, A.J.; Howland ,C.J, A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder", IEEE J. Solid-State Circuits, Vol.37, Iss.3, Mar 2002 Pages:404-412
7. K. Gunnam, G. Choi and M. B. Yeary, "An LDPC decoding schedule for memory access reduction," IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, pp-173-6 vol. 5, May 2004.
8. M. Karkooti and J. Cavallaro, "Semi-parallel reconfigurable architectures for real-time LDPC decoding," Proceedings of International Conference on Information Technology, Coding and Computing, vol. 1, pp. 579-585, 2004.
9. T. Brack, F. Kienle and N. Wehn. "Disclosing the LDPC Code Decoder Design Space", Design Automation and Test in Europe (DATE) Conference, pp. 200-205, March 2006.
10. "Part 16: air interface for fixed and mobile broadband wireless access systems amendment for physical and medium access control layers for combined fixed and mobile operation in licensed bands", IEEE P802.16e-2005, October 2005
11. K. Gunnam, W. Wang, E. Kim, G. Choi and M.B. Yeary, "Decoding of Quasi-cyclic LDPC Codes using On-The-Fly Computation," Accepted for 40th Asilomar Conf. on Signals, Systems and Computers, October 2006.
12. K. Gunnam and G. Choi, "A Low Power Architecture for Min-Sum Decoding of LDPC Codes," TAMU, ECE Technical Report, May, 2006, TAMU-ECE-2006-02. [Online]. Available: http://dropzone.tamu.edu/tehpubs.
13. L. Yang; M. Shen; H. Liu, and C. Shi, "An FPGA implementation of low-density parity-check code decoder with multi-rate capability," Proceedings of the Asia and South Pacific Design Automation Conference, .pp. 760- 763 Vol. 2, 18-21 Jan. 2005
14. H. Zhong and T. Zhang, "Block-LDPC: A practical LDPC coding system design approach", IEEE Trans. on Circuits and Systems I,vol. 52, no. 4, pp. 766-775, April, 2005
15. G. Malema and M. Liebelt, "Interconnection Network for Structured Low-Density Parity-Check Decoders," Asia-Pacific Conference on ,Communications, vol., no.pp. 537-540, 03-05 Oct. 2005
16. K. Gunnam, G. Choi, M. B. Yeary and M.Atiquzzaman, "VLSI architectures for layered decoding for irregular LDPC codes of WiMax", TAMU, ECE Technical Report, July 2006, TAMU-ECE-2006-08.
17. K. Gunnam, "Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation," PhD Dissertation, Texas A&M University, October 2006.