An LDPC decoding schedule for memory access reduction

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 5, Issue , 2004, Pages

  Gunnam, Kiran ^a   Choi, Gwan ^a   Yeary, Mark ^a,b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b UNIVERSITY OF OKLAHOMA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOW DENSITY PARITY CHECK CODES (LDPC); RANDOM BIT FILLING ALGORITHMS; SHANON LIMIT CODES;

ALGORITHMS; CODES (SYMBOLS); DATA TRANSFER; MATRIX ALGEBRA; STATIC RANDOM ACCESS STORAGE;

ENCODING (SYMBOLS);

EID: 4544293904     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. R. G. Gallager, Low-Density Parity-Check Codes, M.I.T Press, 1963. Available at http://justice.mit.edu/people/gallager.html
2. Blanksby, A.J.; Rowland, C.J, A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder, Solid-State Circuits, IEEE Journal of, Vol.37, Iss.3, Mar 2002 Pages:404-412
3. Yeo, E.; Pakzad, P.; Nikolic, B.; Anantharam, V., "High throughput low-density parity-check decoder architectures" in proceedings of Global Telecommunications Conference, 2001.Volume: 5, Page(s): 3019-3024
4. T. Zhang and K. K. Parhi, "Joint (3, k)-Regular LDPC Code and Decoder/Encoder Design", to appear in IEEE Transactions on Signal Processing. Available at http://www.ecse.rpi.edu/homepages/tzhang/
5. A. Selvarathinam, G.Choi, K. Narayanan, A.Prabhakar, E. Kim, "A Massively Scalable Decoder Architecture for Low-Density Parity-Check Codes", in proceedings of ISCAS'2003, Bangkok, Thailand.
6. A. Selvarathinam, G.Choi, K. Narayanan, A.Prabhakar, E. Kim, "A Massively Scalable Decoder Architecture for Low-Density Parity-Check Codes". Journal version in submission.
7. M. M. Mansour and N. R. Shanbhag, "Low Power VLSI Decoder Architectures for LDPC codes," in proceedings of International Symposium on Low Power Electronics and Design (ISLPED), Monterey, CA, Aug. 2002, pp. 284-289.
8. M. M. Mansour, M. M. Mansour, and N. R. Shanbhag, "A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes," in proceedings of IEEE Workshop on Signal Processing Systems (SiPS), Seoul, Korea, August 2003