Semi-parallel reconfigurable architectures for real-time LDPC decoding

International Conference on Information Technology: Coding Computing, ITCC

Volumn 1, Issue , 2004, Pages 579-585

  Karkooti, Marjan ^a   Cavallaro, Joseph R ^a  

^a Rice University   (United States)

Author keywords

Area time tradeoffs; Channel coding; FPGA implementation; Parallel architecture; Reconfigurable architecture

Indexed keywords

AREA-TIME TRADEOFFFS; CHANNEL CODING; FPGA IMPLEMENTATION; PARALLEL ARCHITECTURE; RECONFIGURABLE ARCHITECTURE;

CODES (SYMBOLS); COMPUTER NETWORKS; COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; DECODING; FIELD PROGRAMMABLE GATE ARRAYS; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS;

COMPUTER ARCHITECTURE;

EID: 3042599472     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITCC.2004.1286526     Document Type: Conference Paper

References (11)

1. A. Blanksby and C. Howland. A 690-mW 1-Gbps 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder. Journal of Solid State Circuits, 37(3):404-412, Mar 2002.
2. Y. Chen and D. Hocevar. A FPGA and ASIC Implementation of Rate 1/2 8088-b Irregular Low Density Parity Check Decoder. IEEE Global Telecommunications Conference, GLOBECOM, 2003.
3. S. Chung, T. Richardson, and R. Urbanke. Analysis of Sum-Product Decoding of Low-Density Parity-Check Codes Using a Gaussian Approximation. IEEE Trans. on Inform. Theory, 47(2):657-670, Feb 2001.
4. R. Gallager. Low-Density Parity-Check Codes. IRE Trans. on Inform. Theory, 8:21-28, Jan 1962.
5. J. Heo. Analysis of Scaling Soft Information on Low Density Parity Check Codes. Elect. Letters, 39(2):219-221, Jan 2003.
6. L. Lee. LDPC Code, Application to the Next Generation Wireless Communication Systems, 2003. Fall VTC, Panel Pres. by Hughes Network.
7. D. MacKay and R. Neal. Near Shannon Limit Performace of Low Density Parity Check codes. In Elec. Letters, volume 32, pages 1645-6, Aug 1996.
8. M. Mansour and N.Shanbhag. Low Power VLSI Decoder Architectures for LDPC Codes. Proc. of the Int. Symp. on Low Power Electronics and Design., pages 284-289, 2002.
9. Y. Mao and A. Banihashemi. A Heuristic Search for Good Low-Density Parity-Check Codes at Short Block Lengths. IEEE Int. Conf. on Comm., pages 41-44, Jun 2001.
10. T. R. R. Urbanke. Efficient Encoding of Low-Density Parity Check Codes. IEEE Trans. on Inform. Theory, 47(2):638-656, Feb 2001.
11. T. Zhang. Efficient VLSI Architectures for Error-Correcting Coding. PhD thesis, University of Minnesota, Jul 2002.