-
1
-
-
0033099611
-
Good error-correcting codes based on very sparse matrices
-
March
-
D.J.C. McKay, "Good error-correcting codes based on very sparse matrices," IEEE Trans. on Info. Theory, vol. IT-45, pp. 399-431, March 1999.
-
(1999)
IEEE Trans. on Info. Theory
, vol.IT-45
, pp. 399-431
-
-
McKay, D.J.C.1
-
2
-
-
0035246127
-
Design of capacity-approaching irregular low-density parity-check codes
-
Feb.
-
T.J. Richardson, M.A. Shokrollahi and R.L. Urbanke, "Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes," IEEE Trans. on Information Theory, vol.47, no.2, pp. 619-637, Feb. 2001.
-
(2001)
IEEE Trans. on Information Theory
, vol.47
, Issue.2
, pp. 619-637
-
-
Richardson, T.J.1
Shokrollahi, M.A.2
Urbanke, R.L.3
-
3
-
-
0035150335
-
VLSI implementation-oriented (3,k)-regular low-density parity-check codes
-
Sept.
-
T. Zhang and K.K. Parhi, "VLSI implementation-oriented (3,k)-regular low-density parity-check codes," IEEE Workshop on Signal Processing Systems, Sept. 2001, pp. 25-36.
-
(2001)
IEEE Workshop on Signal Processing Systems
, pp. 25-36
-
-
Zhang, T.1
Parhi, K.K.2
-
4
-
-
0000535066
-
Decoder-first code design
-
Brest, France, Sept.
-
E. Boutillon, J. Castura and F.R. Kschischang, "Decoder-first code design," Proc.: Int'l Symp. on Turbo Codes & Related Topics, Brest, France, Sept. 2000, pp. 459-462.
-
(2000)
Proc.: Int'l Symp. on Turbo Codes & Related Topics
, pp. 459-462
-
-
Boutillon, E.1
Castura, J.2
Kschischang, F.R.3
-
5
-
-
0036504121
-
A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder
-
March
-
A.J. Blanksby and C.J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE J. Solid-State Circuits, vol.37, no.3, pp. 404-412, March 2002.
-
(2002)
IEEE J. Solid-state Circuits
, vol.37
, Issue.3
, pp. 404-412
-
-
Blanksby, A.J.1
Howland, C.J.2
-
6
-
-
0001955815
-
A highly efficient domain-programmable parallel architecture for iterative LDPCC decoding
-
Las Vegas, NV
-
G. Al-Rawi and J. Cioffi, "A highly efficient domain-programmable parallel architecture for iterative LDPCC decoding," Proc.: Int'l Conf. on Info. Technology: Coding and Computing (ITCC), Las Vegas, NV, 2001, pp. 569-577.
-
(2001)
Proc.: Int'l Conf. on Info. Technology: Coding and Computing (ITCC)
, pp. 569-577
-
-
Al-Rawi, G.1
Cioffi, J.2
-
7
-
-
0037633661
-
LDPC code construction with flexible hardware implementation
-
Anchorage, AK, May
-
D.E. Hocevar, "LDPC code construction with flexible hardware implementation," IEEE Int'l Conf. on Comm. (ICC), Anchorage, AK, pp. 2708-2712, May 2003.
-
(2003)
IEEE Int'l Conf. on Comm. (ICC)
, pp. 2708-2712
-
-
Hocevar, D.E.1
-
8
-
-
0842310952
-
A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder
-
San Francisco, CA, Dec.
-
Y. Chen and D. Hocevar, "A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder," IEEE Global Comm. Conf. (Globecom), San Francisco, CA, pp. 113-117, Dec. 2003.
-
(2003)
IEEE Global Comm. Conf. (Globecom)
, pp. 113-117
-
-
Chen, Y.1
Hocevar, D.2
-
9
-
-
0842267569
-
Efficient encoding for a family of quasi-cyclic LDPC codes
-
San Francisco, CA, Dec.
-
D.E. Hocevar, "Efficient encoding for a family of quasi-cyclic LDPC codes," IEEE Global Comm. Conf. (Globecom), San Francisco, CA, pp. 3996-4000, Dec. 2003.
-
(2003)
IEEE Global Comm. Conf. (Globecom)
, pp. 3996-4000
-
-
Hocevar, D.E.1
-
10
-
-
0034318173
-
Parallel concatenated Gallager codes
-
November
-
H. Behairy and S.-C. Chang, "Parallel concatenated Gallager codes," Electronics Letters, vol.36, no.24, pp. 2025-2026, November 2000.
-
(2000)
Electronics Letters
, vol.36
, Issue.24
, pp. 2025-2026
-
-
Behairy, H.1
Chang, S.-C.2
-
11
-
-
0035684626
-
Parallel concatenated Gallager codes for CDMA applications
-
H. Behairy and S.-C. Chang, "Parallel concatenated Gallager codes for CDMA applications," IEEE Global Comm. Conf., (Globecom), 2001, pp. 1002-1006.
-
(2001)
IEEE Global Comm. Conf., (Globecom)
, pp. 1002-1006
-
-
Behairy, H.1
Chang, S.-C.2
-
13
-
-
0032625108
-
A low complexity FEC scheme based on the intersection of interleaved block codes
-
O. Pothier, L. Brunel and J. Boutros, "A low complexity FEC scheme based on the intersection of interleaved block codes," IEEE Vehicular Tech. Conf. (VTC), 1999, pp. 274-278.
-
(1999)
IEEE Vehicular Tech. Conf. (VTC)
, pp. 274-278
-
-
Pothier, O.1
Brunel, L.2
Boutros, J.3
-
14
-
-
4444270737
-
Memory-efficient sum-product decoding of LDPC codes
-
August
-
H. Sankar and K.R. Narayanan, "Memory-efficient sum-product decoding of LDPC codes," IEEE Trans. on Communications, vol. 52, August 2004.
-
(2004)
IEEE Trans. on Communications
, vol.52
-
-
Sankar, H.1
Narayanan, K.R.2
-
15
-
-
0035386013
-
On the performance of turbo product codes over partial response channels
-
July
-
J. Li, E. Kurtas, K.R. Narayanan, and C.N. Georghiades, "On the performance of turbo product codes over partial response channels," IEEE Trans. on Magnetics, vol.37, pp. 1932-1934, July 2001.
-
(2001)
IEEE Trans. on Magnetics
, vol.37
, pp. 1932-1934
-
-
Li, J.1
Kurtas, E.2
Narayanan, K.R.3
Georghiades, C.N.4
-
16
-
-
0035687731
-
Generalized product accumulate codes: Analysis and performance
-
J. Li, K.R. Narayanan, and C.N. Georghiades, "Generalized product accumulate codes: analysis and performance," IEEE Global Comm. Conf. (Globecom), 2001, pp. 975-979.
-
(2001)
IEEE Global Comm. Conf. (Globecom)
, pp. 975-979
-
-
Li, J.1
Narayanan, K.R.2
Georghiades, C.N.3
-
17
-
-
0036971714
-
Turbo decoder architectures for low-density parity check codes
-
Nov.
-
M.M. Mansour and N.R. Shanbhag, "Turbo decoder architectures for low-density parity check codes," IEEE Global Comm. Conf. (Globecom), Nov. 2002, pp. 1383-1388.
-
(2002)
IEEE Global Comm. Conf. (Globecom)
, pp. 1383-1388
-
-
Mansour, M.M.1
Shanbhag, N.R.2
|