An FPGA implementation of low-density parity-check code decoder with multi-rate capability

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 760-763

  Yang, Lei ^a   Shen, Manyuan ^a   Liu, Hui ^a   Shi, C J Richard ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CODING; COMPUTER AIDED DESIGN; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FORWARD ERROR CORRECTION; SIGNAL ENCODING; SIGNAL TO NOISE RATIO;

ERROR CORRECTION CAPABILITY; FPGA IMPLEMENTATIONS; INTERFERENCE CONDITION; LOW DENSITY PARITY CHECK; LOW-DENSITY PARITY-CHECK (LDPC) CODES; MULTI-RATE CAPABILITY; WIRELESS APPLICATION; WIRELESS TELECOMMUNICATIONS;

DECODING;

EID: 33645828541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1121011     Document Type: Conference Paper

References (8)

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