메뉴 건너뛰기




Volumn 4727 LNCS, Issue , 2007, Pages 427-442

Information theoretic evaluation of side-channel resistant logic styles

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; CRYPTOGRAPHY; SYSTEMS ANALYSIS;

EID: 38049074795     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-74735-2_29     Document Type: Conference Paper
Times cited : (53)

References (26)
  • 1
    • 35248817849 scopus 로고    scopus 로고
    • Agrawal, D., Archambeault, B., Rao, J., Rohatgi, P.: The EM Side-Channel(s). In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C (eds.) CHES 2002. LNCS, 2523, pp. 29-45. Springer, Heidelberg (2003)
    • Agrawal, D., Archambeault, B., Rao, J., Rohatgi, P.: The EM Side-Channel(s). In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C (eds.) CHES 2002. LNCS, vol. 2523, pp. 29-45. Springer, Heidelberg (2003)
  • 2
    • 0035275045 scopus 로고    scopus 로고
    • Dynamic Current Mode Logic (DyCML): A New LowPower High-Performances Logic Styles
    • Allam, M.W., Elmasry, M.I.: Dynamic Current Mode Logic (DyCML): A New LowPower High-Performances Logic Styles. IEEE Journal of Solid State Circuits 36(3), 550-558 (2001)
    • (2001) IEEE Journal of Solid State Circuits , vol.36 , Issue.3 , pp. 550-558
    • Allam, M.W.1    Elmasry, M.I.2
  • 3
    • 33750722766 scopus 로고    scopus 로고
    • Archambeau, C., Peeters, E., Standaert, F.-X., Quisquater, J.-J.: Template Attacks in Principal Subspaces. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, 4249, pp. 1-14. Springer, Heidelberg (2006)
    • Archambeau, C., Peeters, E., Standaert, F.-X., Quisquater, J.-J.: Template Attacks in Principal Subspaces. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 1-14. Springer, Heidelberg (2006)
  • 4
    • 38049023783 scopus 로고    scopus 로고
    • Department of of Electrical Engineering and Computer Science, University of California, Berkeley
    • Berkley MOSFET Simulation Model: Device Research Group, Department of of Electrical Engineering and Computer Science, University of California, Berkeley, http://www-device.eecs.berkeley.edu/bsim3/
    • Berkley MOSFET Simulation Model: Device Research Group
  • 5
    • 35248899532 scopus 로고    scopus 로고
    • Chari, S., Rao, J., Rohatgi, P.: Template Attacks. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C (eds.) CHES 2002. LNCS, 2523, pp. 13-28. Springer, Heidelberg (2003)
    • Chari, S., Rao, J., Rohatgi, P.: Template Attacks. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C (eds.) CHES 2002. LNCS, vol. 2523, pp. 13-28. Springer, Heidelberg (2003)
  • 7
    • 38049070048 scopus 로고    scopus 로고
    • http ://www.mentor.com/products/eldo
  • 8
    • 35248826454 scopus 로고    scopus 로고
    • Fournier, J.A., Moore, S., Li, H., Mullins, R.D., Taylor, G.S.: Security Evaluation of Asynchronous Circuits. In: D.Walter, C., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, 2779, pp. 137-151. Springer, Heidelberg (2003)
    • Fournier, J.A., Moore, S., Li, H., Mullins, R.D., Taylor, G.S.: Security Evaluation of Asynchronous Circuits. In: D.Walter, C., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 137-151. Springer, Heidelberg (2003)
  • 9
    • 27244432772 scopus 로고    scopus 로고
    • Fischer, W., Gammel, B.M.: Masking at the Gate Level in The Presence of Glitches. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, 3659, pp. 187-200. Springer, Heidelberg (2005)
    • Fischer, W., Gammel, B.M.: Masking at the Gate Level in The Presence of Glitches. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 187-200. Springer, Heidelberg (2005)
  • 10
    • 27244444584 scopus 로고    scopus 로고
    • Guilley, S., Hoogvorst, P., Mathieu, Y., Pacalet, R.: The Backend Duplication Method: A Leakage-Proof Place-and-Route Strategy for ASICs. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, 3659, pp. 383-397. Springer, Heidelberg (2005)
    • Guilley, S., Hoogvorst, P., Mathieu, Y., Pacalet, R.: The Backend Duplication Method: A Leakage-Proof Place-and-Route Strategy for ASICs. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 383-397. Springer, Heidelberg (2005)
  • 11
    • 33745915554 scopus 로고    scopus 로고
    • Low-swing current mode logic (LSCML): A new logic style for secure smart cards against power analysis attacks
    • Hassoune, I., Macé, F., Flandre, D., Legat, J.-D.: Low-swing current mode logic (LSCML): a new logic style for secure smart cards against power analysis attacks. Microelectronics Journal 37(9), 997-1006 (2006)
    • (2006) Microelectronics Journal , vol.37 , Issue.9 , pp. 997-1006
    • Hassoune, I.1    Macé, F.2    Flandre, D.3    Legat, J.-D.4
  • 12
    • 84943632039 scopus 로고    scopus 로고
    • Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS and Other Systems
    • Koblitz, N, ed, CRYPTO 1996, Springer, Heidelberg
    • Kocher, P.: Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS and Other Systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104-113. Springer, Heidelberg (1996)
    • (1996) LNCS , vol.1109 , pp. 104-113
    • Kocher, P.1
  • 13
    • 84939573910 scopus 로고    scopus 로고
    • Differential Power Analysis
    • Wiener, M.J, ed, CRYPTO 1999, Springer, Heidelberg
    • Kocher, P., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M.J. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 398-412. Springer, Heidelberg (1999)
    • (1999) LNCS , vol.1666 , pp. 398-412
    • Kocher, P.1    Jaffe, J.2    Jun, B.3
  • 14
    • 27244458099 scopus 로고    scopus 로고
    • Li, H., Markettos, T., Moore, S.: Security Evaluation Against Electromagnetic Analysis at Design Time. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, 3659, pp. 280-292. Springer, Heidelberg (2005)
    • Li, H., Markettos, T., Moore, S.: Security Evaluation Against Electromagnetic Analysis at Design Time. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 280-292. Springer, Heidelberg (2005)
  • 15
    • 33646419370 scopus 로고    scopus 로고
    • A Dynamic Current Mode Logic to Counteract Power Analysis Attacks
    • Bordeaux France, pp, November
    • Macé, F., Standaert, F.-X., Hassoune, I., Legat, J.-D., Quisquater, J.-J.: A Dynamic Current Mode Logic to Counteract Power Analysis Attacks. In: The Proceedings DCIS 2004, Bordeaux France, pp. 186-191 (November 2004)
    • (2004) The Proceedings DCIS , pp. 186-191
    • Macé, F.1    Standaert, F.-X.2    Hassoune, I.3    Legat, J.-D.4    Quisquater, J.-J.5
  • 16
    • 24144459808 scopus 로고    scopus 로고
    • Mangard, S., Popp, T., Gammel, B.: Side-Channel Leakage of Masked CMOS Gates. In: Menezes, A.J. (ed.) CT-RSA 2005. LNCS, 3376, pp. 351-365. Springer, Heidelberg (2005)
    • Mangard, S., Popp, T., Gammel, B.: Side-Channel Leakage of Masked CMOS Gates. In: Menezes, A.J. (ed.) CT-RSA 2005. LNCS, vol. 3376, pp. 351-365. Springer, Heidelberg (2005)
  • 17
    • 27244451515 scopus 로고    scopus 로고
    • Popp, T., Mangard, S.: Masked Dual-Rail Pre-Charge Logic: DPA-Resistance Without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, 3659, pp. 172-186. Springer, Heidelberg (2005)
    • Popp, T., Mangard, S.: Masked Dual-Rail Pre-Charge Logic: DPA-Resistance Without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172-186. Springer, Heidelberg (2005)
  • 18
    • 38049028094 scopus 로고    scopus 로고
    • A Formal Practice-Oriented Model for the Analysis of Side-Channel Attacks. Cryptology ePrint Archive
    • Report 2006/139
    • Standaert, F.-X., Malkin, T.G., Yung, M.: A Formal Practice-Oriented Model for the Analysis of Side-Channel Attacks. Cryptology ePrint Archive, Report 2006/139 (2006), http ://eprint.iacr.org
    • (2006)
    • Standaert, F.-X.1    Malkin, T.G.2    Yung, M.3
  • 19
    • 33750693916 scopus 로고    scopus 로고
    • Standaert, F.-X., Peeters, E., Archambeau, C., Quisquater, J.-J.: Towards Security Limits in Side-Channel Attacks. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, 4249, pp. 30-45. Springer, Heidelberg (2006)
    • Standaert, F.-X., Peeters, E., Archambeau, C., Quisquater, J.-J.: Towards Security Limits in Side-Channel Attacks. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 30-45. Springer, Heidelberg (2006)
  • 20
    • 38049036623 scopus 로고    scopus 로고
    • Suzuki, D., Seaki, M.: Security Evaluation of DPA Countermeasures Using DualRail Pre-Charge Logic Style. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, 4249, pp. 255-269. Springer, Heidelberg (2006)
    • Suzuki, D., Seaki, M.: Security Evaluation of DPA Countermeasures Using DualRail Pre-Charge Logic Style. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 255-269. Springer, Heidelberg (2006)
  • 21
    • 84893732023 scopus 로고    scopus 로고
    • Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand DPA on Smart Cards
    • Florence, Italy, pp, September
    • Tiri, K., Akmal, M., Verbauwhede, I.: Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand DPA on Smart Cards. In: The proceedings of ESSCIRC 2002, Florence, Italy, pp. 403-406 (September 2002)
    • (2002) The proceedings of ESSCIRC , pp. 403-406
    • Tiri, K.1    Akmal, M.2    Verbauwhede, I.3
  • 22
    • 3042604811 scopus 로고    scopus 로고
    • A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
    • Paris, France, February
    • Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: The proceedings of DATE 04, Paris, France, vol. 1, pp. 10246-10251 (February 2004)
    • (2004) The proceedings of DATE 04 , vol.1 , pp. 10246-10251
    • Tiri, K.1    Verbauwhede, I.2
  • 23
    • 84902478964 scopus 로고    scopus 로고
    • Place and Route for Secure Standard Cell Design
    • Kluwer, Dordrecht
    • Tiri, K., Verbauwhede, L: Place and Route for Secure Standard Cell Design. In: The proceedings of CARDIS 2004, pp. 143-158. Kluwer, Dordrecht (2004)
    • (2004) The proceedings of CARDIS , pp. 143-158
    • Tiri, K.1    Verbauwhede, L.2
  • 24
    • 33646906840 scopus 로고    scopus 로고
    • Design Method for Constant Power Consumption of Differential Logic Circuits
    • Tiri, K., Verbauwhede, I.: Design Method for Constant Power Consumption of Differential Logic Circuits. In: the proceedings of DATE, pp. 628-633 (2005)
    • (2005) the proceedings of DATE , pp. 628-633
    • Tiri, K.1    Verbauwhede, I.2
  • 25
    • 27944475547 scopus 로고    scopus 로고
    • Tiri, K., Verbauwhede, I.: Simulation Models for Side-Channel Information Leaks. In: The proceedings of DAC 05, pp. 228-233, San Diego, CA, USA, (June 2005)
    • Tiri, K., Verbauwhede, I.: Simulation Models for Side-Channel Information Leaks. In: The proceedings of DAC 05, pp. 228-233, San Diego, CA, USA, (June 2005)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.