SCOPUS 정보 검색 플랫폼

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 246-251

A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation

(2) Tiri, Kris a Verbauwhede, Ingrid a

a Engineering IV (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTO PROCESSORS; DESIGN FLOW; STANDARD CELLS; BUILDING BLOCKES; CONSTANT POWER CONSUMPTION; CRYPTO-PROCESSOR; FPGA DESIGN; FPGA IMPLEMENTATIONS; LOGIC LEVELS; NOVEL DESIGN METHODOLOGY; STANDARD CELL;

AUTOMATION; CAPACITANCE; ENERGY UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DESIGN; MICROPROCESSOR CHIPS; SWITCHING CIRCUITS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC BATTERIES; EXHIBITIONS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN;

EID: 3042604811 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/DATE.2004.1268856 Document Type: Conference Paper

Times cited : (664)

References (9)

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3
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- CHES 2003 , pp. 125-136
- Tiri, K.¹ Verbauwhede, I.²

4
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- A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards
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- ESSCIRC 2002 , pp. 403-406
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5
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- Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
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6
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- Xilinx: Virtex-II Platform FPGAs: Detailed Description. www.xilinx.com/bvdocs/publications/ds031-2.pdf (2002)
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7
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- PN: ADS-XLX-V2-DEV1500
- Avnet Design Services: Xilinx Virtex-II Development Kit. http://www.ads.avnet.com PN: ADS-XLX-V2-DEV1500
- Avnet Design Services: Xilinx Virtex-II Development Kit

8
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- Masking the energy behavior of DES encryption
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- Energy-aware design techniques for differential power analysis protection
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.