Place and route for secure standard cell design

IFIP Advances in Information and Communication Technology

Volumn 153, Issue , 2004, Pages 143-158

  Tiri, Kris ^a   Verbauwhede, Ingrid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Differential Pair; Differential Power Analysis; Place Route; Side Channel Attacks

Indexed keywords

RESEARCH; SMART CARDS;

DIFFERENTIAL PAIRS; DIFFERENTIAL POWER ANALYSIS; DIFFERENTIAL POWER ANALYSIS ATTACK; DIFFERENTIAL ROUTING; NOVEL DESIGN METHODOLOGY; SECURITY APPLICATION; SIDE CHANNEL ATTACK; STANDARD CELL DESIGN;

DESIGN;

EID: 84902478964     PISSN: 18684238     EISSN: None     Source Type: Book Series    
DOI: None     Document Type: Conference Paper

References (12)

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7. K. Tiri, I. Verbauwhede, "A Logic Level design methodology for a secure DPA resistant ASIC or FPGA implementation," Proc. of DATE 2004, pp. 246-251, Feb. 2004.
8. S. Khatri et al. "A novel VLSI layout fabric for deep sub-micron applications," Proc. Of DAC 1999, pp. 491-496, June 1999.
9. Silicon Ensemble, www.cadence.com/products/digita_ic/sepks
10. LEF/DEF Language Reference 5.5, Jan. 2003, www.openeda.org
11. NIST FIPS PUB 46-2 "Data Encryption Standard," Dec. 1993. www.itl.nist.gov/fipspubs/fip46-2.htm
12. Cadence Chip Assembly Router, www.cadence.com/products/custom_ic/chip_assembly