Masking at gate level in the presence of glitches

Lecture Notes in Computer Science

Volumn 3659, Issue , 2005, Pages 187-200

  Fischer, Wieland ^a   Gammel, Berndt M ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Cryptanalysis; Digital circuits; DPA; Glitches; Logic circuits; Masked logic circuits; Masking; Power analysis; Random masking; Side channel attacks

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CRYPTOGRAPHY; DIGITAL CIRCUITS; INFORMATION ANALYSIS; MATHEMATICAL MODELS; RANDOM PROCESSES; SECURITY OF DATA; SET THEORY; SWITCHING;

CRYPTANALYSIS; DPA; GLITCHES; MASKED LOGIC CIRCUITS; POWER ANALYSIS; RANDOM MASKING; SIDE-CHANNEL ATTACKS;

LOGIC CIRCUITS;

EID: 27244432772     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11545262_14     Document Type: Conference Paper

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