Simulation models for side-channel information leaks

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 228-233

  Tiri, Kris ^a   Verbauwhede, Ingrid ^a,b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Countermeasure; Differential Power Analysis; Encryption; Security IC; Side Channel Attack; Simulation Model; Smart Card

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CRYPTOGRAPHY; EMBEDDED SYSTEMS; ENERGY UTILIZATION; GATES (TRANSISTOR); INFORMATION ANALYSIS; SMART CARDS; SWITCHING;

COUNTERMEASURE; DIFFERENTIAL POWER ANALYSIS; SECURITY IC; SIDE-CHANNEL ATTACK (SCA); SIMULATION MODEL;

INTEGRATED CIRCUITS;

EID: 27944475547     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193806     Document Type: Conference Paper

References (21)

1. M. Renaudin, F. Bouesse, P. Proust, J. Tual, L. Sourgen and F. Germain, "High Security Smartcards", DATE, pp. 228-232, February 2004.
2. P. Kocher, R. Lee, G. McGraw, A. Raghunathan, and S. Ravi, "Security as a New Dimension in Embedded System Design", DAC, pp.735-760, June 2004.
3. A. Shamir, and E. Tromer, "Acoustic cryptanalysis", http://www.wisdom.weizmann.ac.il/~tromer/acoustic/, 2004.
4. B. Schneier, "A Hardware DES Cracker", Crypto-Gram Newsletter, http://www.schneier.com/crypto-gram-9808.html#descracker, August 1998.
5. K. Tiri, D. Hwang, A. Hodjat, B. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, "A Side-Channel Leakage Free Coprocessor IC in 0.18μm CMOS for Embedded AES-based Cryptographic and Biometric Processing", DAC, June 2005.
6. P. Kocher, J. Jaffe and B. Jun, "Differential Power Analysis", CRYPTO, LNCS 1666, pp. 388-397, August 1999.
7. T. Messerges, E. Dabbish, and R. Sloan, "Examining smart-card security under the threat of power analysis attacks", IEEE TC, Vol. 51, Issue: 5, pp. 541-552, May 2002.
8. C. Clavier, J. Coron, and N. Dabbous, "Differential Power Analysis in the Presence of Hardware Countermeasures", CHES, LNCS 1965, pp. 252-263, August 2000.
9. A. Shamir, "Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies", CHES, LNCS 1965, pp. 71-77, August 2000.
10. N. Pramstaller, F. Gürkaynak, S. Häne, H. Kaeslin, N. Felber, and W. Fichtner, "Towards an AES Crypto-chip Resistant to Differential Power Analysis", ESSCIRC, pp. 307-310, September 2004.
11. E. Oswald, S. Mangard and N. Pramstaller, "Secure and Efficient Masking of AES - A Mission Impossible?", Report 2004/134 in IACR Cryptology ePrint Archive, June 2004
12. S. Mangard, T. Popp, and B. Gammel, "Side-Channel Leakage of Masked CMOS Gates", CT-RSA, Feb. 2005.
13. K. Tiri, and I. Verbauwhede, "Place and Route for Secure Standard Cell Design", CARDIS, pp. 143-158, August 2004.
14. L. Benini, A. Macii, E. Macii, E. Omerbegovic, F. Pro, et al., "Energy-aware design techniques for differential power analysis protection", DAC, pp. 36-41, June 2003.
15. H. Saputra, N. Vijaykrishnan, M. Kandemir, M. Irwin, R. Brooks, S. Kim, et al., "Masking the energy behavior of DES encryption", DATE, pp. 84-89, March 2003.
16. C. Gebotys "Design of secure cryptography against the threat of power-attacks in DSP-embedded processors", ACM TECS, Vol. 3, Issue 1, pp. 92-113, February 2004.
17. J. Coron, P. Kocher, and D. Naccache, "Statistics and Secret Leakage", FC, LNCS 1962, pp. 157-173, Feb. 2000.
18. J. Coron, "Resistance against differential power analysis for elliptic curve cryptosystems," CHES, LNCS 1717, pp. 292-302, August 1999.
19. K. Tiri and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation", DATE, pp. 246-251, February 2004.
20. S. Mangard, "Hardware Countermeasures Against DPA - A Statistical Analysis of Their Effectiveness", CT-RSA, LNCS 2964, pp. 222-235, February 2004.
21. F. Mace, F. Standaert, I. Hassoune, J. Legat and J. Quisquater, "A Dynamic Current Mode Logic to Counteract Power Analysis Attacks", DCIS, November 2004