Security evaluation of asynchronous circuits

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2779, Issue , 2003, Pages 137-151

  Fournier, Jacques J A ^a   Moore, Simon ^b   Li, Huiyun ^b   Mullins, Robert ^b   Taylor, George ^b  

^a GEMPLUS   (France)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

Asynchronous circuits; Design time security evaluation; Dual Rail encoding; EMA; Fault Analysis; Power Analysis

Indexed keywords

DESIGN; ELECTRIC NETWORK ANALYSIS; EMBEDDED SYSTEMS; RECONFIGURABLE HARDWARE; SIDE CHANNEL ATTACK; SMART CARDS;

ASYNCHRONOUS CIRCUITS; DESIGN TIME SECURITY EVALUATION; DUAL RAIL ENCODING; FAULT ANALYSIS; POWER ANALYSIS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 35248826454     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45238-6_12     Document Type: Review

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