Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

Microelectronics Journal

Volumn 37, Issue 9, 2006, Pages 997-1006

  Hassoune, Ilham ^a   Mace, Francois ^a   Flandre, Denis ^a   Legat, Jean Didier ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

DPA; Power analysis; Secure smart cards; Self timed logic

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; NETWORKS (CIRCUITS); SECURITY OF DATA;

DIFFERENTIAL POWER ANALYSIS (DPA); DPA; LOW-SWING CURRENT MODE LOGIC (LSCML); POWER ANALYSIS; SECURE SMART CARDS; SELF-TIMED LOGIC;

SMART CARDS;

EID: 33745915554     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2006.01.020     Document Type: Article

References (26)

1. Kocher P.C., Jaffe J., and Jun B. Differential power analysis, Proceedings of CRYPTO 1999 (1999), Springer, Berlin pp. 388-397
2. Messerges T.S., Dabbish E.A., and Sloan R.H. Examining smart-card security under the threat of power analysis attacks. IEEE Trans. Comput. 51 5 (2002) 541-552
3. Tiri K., and Verbauwhede I. Securing encryption algorithms against DPA at the logic level: next generation smart card technology, CHES 2003 (2003), Springer, Berlin pp. 125-136
4. P.C. Kocher, Timing attacks on implementations of Diffie-Helleman, RSA, DSS and other systems, in: The Proceedings of CRYPTO'96, Springer, Berlin, 1996, pp. 104-113.
5. J.J. Quisquater, D. Samyde, Electromagnetic analysis (EMA): measures and counter-measures for smart cards, in: The Proceedings of E-Smart 2001, Springer, Berlin, 2001, pp. 200-210.
6. S. Chari, C.S. Julta, J.R. Rao, R. Rohatgi, Towards sound approaches to counteract power analysis attacks, in: Advances in Cryptology-CRYPTO'99, 19th Annual International Cryptology Conference, August 1999, Lecture Notes in Computer Science, vol. 1666, Springer, Berlin, 1999, pp. 398-412.
7. C. Clavier, J.-S. Coron, N. Dabbous, Differential power analysis in the presence of hardware countermeasures, in: Cryptographic Hardware and Embedded Systems-CHES 2000, Lecture Notes in Computer Science, vol. 1965, Springer, Berlin, 2000, pp. 252-263.
8. C. Karlof, D. Wagner, Hidden Markov Model Cryptanalysis, in Cryptographic Hardware and Embedded Systems-CHES 2003, Lecture Notes in Computer Science, vol. 2779, Springer, Berlin, 2003, pp. 17-34.
9. S. Mangard, T. Popp, B.M. Gammel, Side-channel leakage of masked CMOS gates, in: Topics in Cryptology-CT RSA 2005, Lecture Notes in Computer Science, vol. 3376, Springer, Berlin, 2005, pp. 351-365.
10. Anis M., and Elmasry M. Multi-Threshold CMOS Digital Circuits, Managing Leakage Power (2003), Kluwer Academic Publishers, Dordrecht
11. Sokolov D., Murphy J., Bystrov A., and Yakovlev A. Design and analysis of dual-rail circuits for security applications. IEEE Trans. Comput. 54 4 (2005) 449-459
12. S. Moore, R. Anderson, P. Cunningham, R. Mullins, G. Taylor, Improving smart card security using self-timed circuits, Proceedings of the International Symposium on Asynchronous Circuits and Systems (ASYNC), 2002, pp. 211-218.
13. Z. Yu, S. Furber, L. Plana, An investigation into the security of self-timed circuits, Proceedings of the International Symposium on Asynchronous Circuits and Systems (ASYNC), 2003, pp. 206-215.
14. In: Piguet C. (Ed). Low-power Electronics Design (2004), CRC Press, Boca Raton, FL
15. J. Schutz, A 3.3 V 0.6 μm BiCMOS superscalar microprocessor, ISSCC Dig. Technical Papers, 1994, pp. 202-203.
16. S. Rajgopal, Challenges in low-power microprocessor design, Proceedings of the Ninth International Conference on VLSI Design: VLSI in Mobile Communication, January 1996, pp. 329-330.
17. J.D. Garside, A CMOS VLSI Implementation of an asynchronous Alu, in: Proceedings of the IFIP Conference on Asynchronous Design Methodologies, Manchester, England, March 1993, pp. 181-192.
18. Allam M.W., and Elmasry M.I. Dynamic current mode logic (DyCML): a new low-power high-performance logic style. IEEE J. Solid-State Circuits 36 3 (2001) 550-558
19. E. Brier, C. Clavier, Optimal statistical power analysis, IACR e-print archive 2003/152, 2003 〈http://eprint.iacr.org〉.
20. K. Tiri, M. Akmal, I. Verbauwhede, A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards, in: The Proceedings of ESSCIRC 2002, 2002, pp. 403-406.
21. F. Mace, F.-X. Standaert, I. Hassoune, J.-D. Legat, J.-J. Quisquater, A dynamic current mode logic to counteract power analysis attacks, in: The Proceedings of DCIS 2004, 2004, pp. 186-191.
22. P. Barreto, V. Rijmen, The Khazad legacy-level block cipher available from 〈http://paginas.terra.com.br/informatica/paulobarreto/KhazadPage.html〉.
23. Shannon C.E. Communication theory of secrecy systems. Bell Systems Technical J. 28 (1949) 657-715
24. F. Macé, F.-X. Standaert, J.-J. Quisquater, J.-D. Legat, A design methodology for secured ICs using dynamic current mode logic, 15th International Workshop on Power and Timing Modeling, Optimization and Simulation-PATMOS 2005, Lecture Notes in Computer Science, vol. 3728, Springer, Berlin, 2005, pp. 550-560.
25. Ng P., Balsara P.T., and Steiss D. Performance of CMOS differential circuits. IEEE J. Solid-State Circuits 31 6 (1996) 841-846
26. Koren I. Computer Arithmetic Algorithms (1993), Prentice-Hall, Englewood-Cliffs, NJ