A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 11, 2006, Pages 1250-1254

  Jones, Alex K ^a   Hoare, Raymond ^a   Kusic, Dara ^a   Stander, Justin ^a   Mehta, Gayatri ^a   Fazekas, Josh ^a  

^a University of Pittsburgh   (United States)

Author keywords

Combinational; hardware functions; very large instruction word (VLIW)

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; PROGRAM PROCESSORS;

HARDWARE FUNCTIONS; MULTICORE EMBEDDED PROCESSOR ARCHITECTURE; VERY LARGE INSTRUCTION WORD;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 37849185922     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.882849     Document Type: Article

References (22)

1. F. Karim, A. Mellan, A. Nguyen, U. Aydonat, and T. Abdelrahman, “A multilevel computing architecture for embedded multimedia applications, ” IEEE Micro, vol. 24, no. 3, pp. 56–66, May-Jun. 2004.
2. R. Kumar, D. M. Tullsen, N. P. Jouppi, and P. Ranganathan, “Heteroge-nous chip multiprocessors, ” IEEE Comput., vol. 33, no. 11, pp. 32–38, Nov. 2005.
3. D. Pham et al., “The design and implementation of a first-generation CELL processor, ” in Dig. Tech. Papers Int. Solid-State Circuits Conf. (ISSCC), Feb. 8–10, 2005, vol. 1, pp. 182–183.
4. B. Khailany et al., “Imagine: Media processing with streams, ” IEEE Micro, vol. 21, no. 2, pp. 35-46, Mar.-Apr. 2001.
5. B. Khailany, W. J. Dally, A. Chang, U. J. Kapsi, J. Namkoong, and B. Towles, “VLSI design and verification of the imagine processor, ” in Proc. IEEE Int. Conf. Comput. Design (ICCD), Sep. 16–18, 2002, pp. 289–294.
6. D. Kusic, R. Hoare, A. K. Jones, J. Fazekas, and J. Foster, “Extracting speedup from C-code with poor instruction-level parallelism, ” in Proc. Workshop of Massively Parallel Processing (WMPP), 2005, p. 264.
7. M. Sima, S. Cotofana, J. T. J. van Eijndhoven, S. Vassilidis, and K. Vissers, “An 8×8 IDCT implementation on an FPGA-augmented tri-media, ” in Proc. IEEE Symp. Field-Programmable Custom Computing Machine (FCCM), 2001, pp. 160–169.
8. T. J. Callahan, J. R. Hauser, and J. Wawrzynek, “The Garp architecture and C compiler, ” IEEE Comput., vol. 33, no. 4, pp. 62–69, Apr. 2000.
9. S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao, “The Chimaera reconfigurable functional unit, ” in Proc. IEEE Symp. Field-Pro-grammable Custom Computing Machine (FCCM), 1997, pp. 87–96.
10. S. Dutta, A. Wolfe, W. Wolf, and K. O’Connor, “Design issues for very long-instruction-word VLSI video signal processors, ” in Proc. IEEE Workshop VLSI Signal Process., 1996, pp. 95–104.
11. H. Schmit, D. Whelihan, A. Tsai, M. Moe, B. Levine, and R. R. Taylor, “Piperench: A virtualized programmable datapath in 0.18-µm technology, ” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), May 12–15, 2002, pp. 63–66.
12. B. A. Levine and H. Schmit, “Efficient application representation for HASTE: Hybrid architectures with a single, transformable executable, ” in Proc. IEEE Symp. Field-Programmable Custom Computing Machine (FCCM), Apr. 9–11, 2003, pp. 101–110.
13. C. Ebeling, D. C. Cronquist, and P. Franklin, “RaPiD—Reconfigurable pipelined datapath, ” in Proc. Int. Workshop Field-Programmable Logic and Applications, Darmstadt, Germany, 1996.
14. E. Mirsky and A. Dehon, “MATRIX: A reconfigurable computing architecture with configurable instruction distribution and deployable resources, ” in Proc. IEEE Symp. FPGAs for Custom Computing Machines, Apr. 17–19, 1996, pp. 157–166.
15. Z. Huang, S. Malik, N. Moreano, and G. Araujo, “The design of dynamically reconfigurable datapath coprocessors, ” ACM Trans. Embedded Comput. Syst. (TECS), vol. 3, no. 2, pp. 361–384, 2004.
16. A. Jones, R. Hoare, I. Kourtev, J. Fazekas, D. Kusic, J. Foster, S. Boddie, and A. Muaydh, “A 64-way VLIW/SIMD FPGA processing architecture and design flow, ” in Proc. IEEE Int. Conf. Electron. Circuits Syst. (ICECS), Dec. 13–15, 2004, pp. 599–602.
17. R. Hoare, A. K. Jones, D. Kusic, J. Fazekas, J. Foster, S. Tung, and M. McCloud, “Rapid VLIW processor customization for signal processing applications using combinational hardware functions, ” EURASIP J. Appl. Signal Process., vol. 2006, pp. 1–23, 2006, 54473.
18. A. K. Jones, R. Hoare, D. Kusic, J. Fazekas, and J. Foster, “An FPGA based VLIW processor with custom hardware execution, ” in Proc. ACM FPGA Symp., Monterey, CA, 2005.
19. V. Chaiyaku and D. D. Gayski, Assignment decision diagram for high-level synthesis Univ. of California, Irvine, Tech. Rep. 92–103, Dec. 1992.
20. V. Chaiyakul, D. D. Gayski, and L. Ramachandran, “High-level transformations for minimizing syntactic variances, ” in Proc. Design Autom. Conf. (DAC), Jun. 14–18, 1993, pp. 413–418.
21. C. Lee, M. Potkonjak, and W. K. Magione-Smith, “Mediabench: A tool for evaluating and synhesizing multimedia and communications systems, ” in Proc. IEEE/ACM Int. Symp Microarchitecture (MICRO), Research Triangle Park, NC, 1997.
22. T. Austin, E. Larson, and D. Ernst, “Simplescalar: An infrastructure of computer system modeling, ” IEEE Comput., vol. 35, no. 2, pp. 59–67, Feb. 2002.