Extracting speedup from C-code with poor instruction-level parallelism

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Kusic, Dara ^a   Hoare, Raymond ^a   Jones, Alex K ^a   Fazekas, Joshua ^a   Foster, John ^a  

^a University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL ACCELERATORS; INSTRUCTION-LEVEL PARALLELISM (ILP); SINGLE-INSTRUCTION MULTIPLE-DATA (SIMD); VERY LONG INSTRUCTION WORD (VLIW);

BINARY CODES; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; MULTIMEDIA SYSTEMS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS;

SUPERVISORY AND EXECUTIVE PROGRAMS;

EID: 33746314859     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.216     Document Type: Conference Paper

References (15)

1. R. Hoare, A.K. Jones, D. Kusic, J. Fazekas, J. Foster, S. Tung and M. McCloud, "Rapid VLIW Processor Customization For Signal Processing Applications Using Combinational Hardware Functions," Int. Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb. 2005.
2. P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Chang, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, "MATCH: A MATLAB Compilation Environment for Configurable Computing Systems," International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2000.
3. S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau, "SPARK: A High-Level Synthesis Framework For Applying Parallelizing Compiler Transformations," in Proc. of the International Conference on VLSI Design, January 2003.
4. A. K. Jones, D. Bagchi, S. Pal, P. Banerjee, and A. Choudhary, "Pact HDL: Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations," in Power Aware Computing, pp. 169-190. Kluwer Academic Publishers, Boston, MA, 2002.
5. Synopsys, Inc., "Behavioral Compiler," http://www.synopsys.com.
6. E. Atzori, S.M. Carta and L. Raffo, "44.6% Processing Cycles Reduction in GSM Voice by Low-power Reconfigurable Co-processor Architecture," Eletronics Letters, Vol. 38 No. 24, November 2002, pp. 1524-1526.
7. R. Garg, C.Y. Chung, D. Kim and Y. Kim, "Boundary Macroblock Padding in MPEG-4 Video Decoding Using a Graphics Co-processor," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 12 No. 8, August 2002, pp. 719-723.
8. T. Bridges, S.W. Kitchel and R. M. Wehrmeister, "A CPU Utilization Limit for Massively Parallel MIMD Computers," Fourth Symposium on the Frontiers of Massively Parallel Computation, McLean, VA, October 1992.
9. S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. Taylor, "PipeRench: A Reconfigurable Architecture and Compiler" in IEEE Computer, Vol.33, No. 4, April 2000.
10. B. A. Levine, H. Schmit, "Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable." FCCM 2003.
11. C. Ebeling, D. C. Cronquist, P. Franklin, "RaPiD - Reconfigurable Pipelined Datapath", in the 6th International Workshop on Field-Programmable Logic and Applications, 1996.
12. E. Mirsky and A. DeHon," MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources", in Proc. of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1996.
13. U.J. Kapasi, W.J. Dally, S. Rixner, J.D. Owens, B. Khailany, "The Imagine Stream Processor", IEEE International Conference on Computer Design: VLSI in Computers and Processors, Sept. 2002.
14. T.J. Callahan, J.R. Hauser and J. Wawrzynek, "The Garp architecture and C compiler," Computer, Volume: 33, Issue: 4, April 2000.
15. S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao, "The Chimaera Reconfigurable Functional Unit," IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, 1997.