A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs

Proceedings - SBCCI 2007: 20th Symposium on Integrated Circuits and System Design

Volumn , Issue , 2007, Pages 282-287

  Barcelos, Daniel ^a   Brião, Eduardo W ^a   Wagner, Flávio R ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Energy; Memory organization; MPSoC; NoC; Task migration

Indexed keywords

CODES (SYMBOLS); DISTRIBUTED COMPUTER SYSTEMS; ELECTRIC POWER UTILIZATION; STORAGE ALLOCATION (COMPUTER);

CODE TRANSFER ENERGY; DISTRIBUTED MEMORY ALTERNATIVES; TASK MIGRATION;

HYBRID INTEGRATED CIRCUITS;

EID: 37849011608     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1284480.1284557     Document Type: Conference Paper

References (24)

1. T. AlEnawy, H. Aydin. Energy-aware Task Allocation for Rate Monotonie Scheduling. In: IEEE Real-time and Embedded Technology and Applications Symposium, San Francisco, California, pp. 213-223, 2005.
2. L. Benini, G. DeMicheli. Networks on chips: a new SoC paradigm. IEEE Computer, vol.35, n.1, pp. 70-78. 2002.
3. R. Bergamaschi, W. Lee. Designing System-on-Chip using Cores. In: 37 th Design Automation Conference (DAC), USA, 2000, pp. 420-425.
4. S. Bertozzi, A. Acquaviva, D. Bertozzi, A. Poggiali. Supporting Task Migration in Multi-processor Systems-on-chip: a Feasibility Study. In: Design, Automation and Test in Europe Conference (DATE), pp. 15-20, Munich, Germany, 2006.
5. J. Butts, G. Shoi. A Static Power Model for Architects. In: International Symposium on Microarchitecture, ACM Press, California, 2000, 191-201.
6. W. J. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, DAC 2001, p684-689.
7. T. Grötker et al. System design with SystemC. Boston: Kluwer Academic Publishers, 2002.
8. J. Hu, R. Marculescu. Energy-Aware Communication and Task Scheduling for Network-on-chip Architectures under Real-Time Constraints. In: Design, Automation and Test in Europe (DATE), pp. 234-239, Munich, Germany, 2004.
9. S. A. Ito, L. Carro, R. P. Jacobi. Making Java work for microcontroller applications. Design & Test of Computers, IEEE Volume 18, Issue 5, Sept.-Oct. 2001 Page(s): 100 -110.
10. A. Jalabert et al. XpipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. In: Design, Automation and Test in Europe Conference (DATE), 2004.
11. M. Kandemir, G. Chen. Locality-Aware Process Scheduling for Embedded MPSoCs. In: Design, Automation and Test in Europe Conference (DATE), pp. 870-875, 2005.
12. F. Li, M. Kandemir. Locality-conscious Workload Assignment for Array-based Computations in MPSOC Architectures. In: Design Automation Conference (DAC), pp. 95-100, 2005.
13. J-Y. Mignolet et al., Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip, Proc. DATE 2003, pp.986-992.
14. D. Milojicic, F. Douglis, Y. Paindaveine, R. Wheeler, S. Zhou. Process Migration Survey. ACM Computing Surveys, September 2000.
15. V. Nollet, T. Marescaux, P. Avasare, J-Y. Mignolet, D. Verkest. Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles, In: Design, Automation and Test in Europe Conference (DATE), pp 252-253, Munich, Germany, 2005.
16. V. Nollet, et al. Low Cost Task Migration Initiation in a Heterogeneous MP-SoC In: Design, Automation and Test in Europe Conference (DATE), pp. 252-253, 2005.
17. V. Nollet, et al. Operating-System Controlled Network on Chip. DAC, pp. 256-259, 2004.
18. O. Ozturk et all. Selective Code/Data Migration for Reducing Communication Energy in Embedded MpSoC Architectures. In: 6th ACM Great Lakes symposium on VLSI GLSVLSI '06. April 2006.
19. P. Sinha. Distributed Operating Systems: Concepts and Design. IEEE Press. New York, 1996.
20. F. Wronski, E. Brião, F. R. Wagner. Evaluating Energy-Aware Task Allocation Strategies for MPSoCs. In: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES). Braga, Portugal, October 2006.
21. H. Wang. Orion: A Power-performance Simulator for Interconnection Networks. In: ACM MICRO. Istanbul, Turkey, pp. 294-305. 2002.
22. T. Ye, G. DeMicheli, L. Benini. Analysis of Power Consumption on Switch Fabrics in Network Routers. In: Design Automation Conference (DAC), pp 524-529, 2002.
23. C. Zeferino, A. Susin. SoCIN: a Parametric and Scalable Network-on-Chip. In: Symposium on Integrated Circuits and Systems Design (SBCCI), pp.169-174 , 2003.
24. J. Zhuo, and C. Chakrabarti. An Efficient Dynamic Task Scheduling Algorithm for Battery Powered DVS Systems In: Design Automation Conference Asia and South Pacific (ASP-DAC), pp.846-849, 2005.