IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology

IBM Journal of Research and Development

Volumn 46, Issue 4-5, 2002, Pages 631-644

  Curran, Brian W ^a   Chan, Yuen H ^a   Wu, Philip T ^a   Camporese, Peter J ^a   Northrop, Greg A ^b   Hatch, Robert F ^a   Lacey, Lisa Bryant ^b   Eckhardt, James P ^a   Hui, David T ^a   Smith, Howard H ^a  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS;

MULTICHIP MODULE (MCM);

SERVERS;

EID: 0036663757     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.464.0631     Document Type: Article

References (21)

1. B. Curran, P. Camporese, S. Carey, Y. Chan, R. Clemen, R. Crea, D. Hoffman, T. Koprowski, M. Mayo, T. McPherson, G. Northrop, L. Sigal, H. Smith, F. Tanzi, and P. Williams, "A 1.1 Ghz First 64B Generation Z900 Microprocessor," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, February 2001, pp. 238-239.
2. S. Crowder, S. Greco, S. Ng, H. Barth, E. Beyer, K. Biery, G. Connolly, J. DeWan, C. Ferguson, R. Chen, X. Hargrove, M. Nowak, E. McLaughlin, P. Purtell, and R. Logan, "0.18μm High-Performance Logic Technology," Symposium on VLSI Technology, Digest of Technical Papers, 1999, pp. 105-106.
3. U. Ghoshal and R. Schmidt, "Refrigeration Technologies for Sub-Ambient Temperature Operation of Computing Systems," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2000, pp. 216-217.
4. L. Sigal, J.D. Warnock, B.W. Curran, Y.H. Chan, P.J. Camporese, M.D. Mayo, W.V. Huott, D.R. Knebel, C.T. Chuang, J.P. Eckhardt, and P.T. Wu, "Circuit Design Techniques for the High-Performance CMOS IBM S/390 Parallel Enterprise Server G4 Microprocessor," IBM J. Res. & Dev. 41, No. 4/5, 489-503 (July/September 1997).
5. A. Pelella, P.F. Lu, Y. Chart, W. Huott, U. Bakhru, S. Kowalczyk, P. Patel, J. Rawlins, and P. Wu, "A 2ns Access, 500MHz 288Kb SRAM Macro," Symposium on VLSI Circuits, Digest of Technical Papers, 1996, pp. 128-129.
6. R. Joshi, S. Kowalczyk, Y. Chan, W. Huott, S. Wilson, and G. Scharff, "A 2 GHz Cycle, 430ps Access Time 34Kb L1 Directory SRAM in 1.5V, 0.18μm CMOS Bulk Technology," Symposium on VLSI Circuits, Digest of Technical Papers, 2000, pp. 222-223.
7. W. Reohr, J. Navarro, Y.H. Chan, Y. Chan, M. Mayo, B. Curran, B. Krumm, A. Pelella, P.F. Lu, U. Bakhru, S. Kowalczyk, J. Rawlins, S. Carey, and P. Wu, "Precharged Cache Hit Logic with Flexible Timing Control," Symposium on VLSI Circuits, Digest of Technical Papers, 1997, pp. 43-44.
8. J.A. Darringer, W.H. Joyner, Jr., C.L. Berman, and L. Trevillyan, "Logic Synthesis Through Local Transformations," IBM J. Res. & Dev. 25, No. 4, 272-280 (July 1981).
9. M. Iyer, L. Stok, and A. Sullivan, "Wavefront Technology Mapping," U.S. Patent 6,334,205, 2001.
10. F. Beeftink, P. Kudva, D. Kung, and L. Stok, "Gate Size Selection for Standard Cell Libraries," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Digest of Technical Papers, 1998, pp. 545-550.
11. F. Beeftink, P. Kudva, D. Kung, R. Puri, and L. Stok, "Combinatorial Cell Design for CMOS Libraries," Integration, the VLSI Journal, pp. 67-93 (February 2000).
12. D. Kung and R. Puri, "Optimal P/N Width Ratio Selection for Standard Cell Libraries," ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Digest of Technical Papers, 1999, pp. 178-184.
13. D. Kung, "A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Digest of Technical Papers, 1998, pp. 352-355.
14. C. Visweswariah and A.R. Conn, "Formulation of Static Circuit Optimization with Reduced Size, Degeneracy and Redundancy by Timing Graph Manipulation," ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Digest of Technical Papers, November 1999, pp. 244-251.
15. A.R. Conn, I.M. Elfadel, W.W. Molzen, Jr., P.R. O'Brien, P.N. Strenski, C. Visweswariah, and C.B. Whan, "Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation," IEEE Design Automation Conference, Digest of Technical Papers, June 1999, pp. 452-459.
16. A.R. Conn, N.I.M. Gould, and Ph. L. Toint, LANCELOT: A Fortran Package for Large-Scale Nonlinear Optimization (Release A), Springer Verlag, New York, 1992.
17. H. Smith, A. Deutsch, S. Mehrotra, D. Widiger, M. Bowen, A. Dansky, G. Kopcsay, and B. Krauter, "R(f)L(f)C Coupled Noise Evaluation of an S/390 Microprocessor Chip," Custom Integrated Circuits Conference, Digest of Technical Papers, May 6-9, 2001, pp. 237-240.
18. K.L. Shepard, V. Narayanan, and R. Rose, "Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits," IEEE Trans. Computer-Aided Design Integrated Circuits & Syst. 18, 1132-1150 (1999).
19. K.L. Shepard and V. Narayanan, "Noise in Deep Submicron Digital Design," IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 1996, pp. 524-531.
20. A. Dansky, H. Smith, and P. Williams, "On-Chip Coupled Noise Analysis of a High Performance S/390 Microprocessor," Electronic Components and Technology Conference, Digest of Technical Papers, 1997, pp. 817-825.
21. C. Ratzlaff and L. Pillage, "RICE: Rapid Interconnect Circuit Evaluation Using AWE," IEEE Trans. Computer-Aided Design Integrated Circuits & Syst. 13, 763-776 (June 1994).