Timing uncertainty measurements on the power5 microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Restle, Phillip J ^a   Franch, Robert L ^a   James, Norman K ^a   Huott, William V ^a   Skergan, Timothy M ^a   Wilson, Steven C ^a   Schwartz, Nicole S ^a   Clabes, Joachim G ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK DISTRIBUTION LATENCY; CLOCK FREQUENCY; CYCLE-TO-CYCLE VARIATIONS; POWER SUPPLY NOISE;

CLOCKS; ELECTRIC DELAY LINES; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; POWER SUPPLY CIRCUITS; PROBABILITY; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; TIMING JITTER; VLSI CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 2442641705     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. P. J. Restle et al, "A Clock Distribution Method for Microprocessors," IEEE J. Solid-State Circuits, vol. 36, pp. 792-799, May 2001.