Enhanced leakage reduction techniques using intermediate strength power gating

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 11, 2007, Pages 1215-1224

  Singh, Harmander ^a,b   Agarwal, Kanak ^a,c   Sylvester, Dennis ^a,b   Nowka, Kevin J ^a,c  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c IBM   (United States)

Author keywords

Bias generation; Low power design; Multiple modes; Power gating

Indexed keywords

BIAS GENERATION; LATCH-TO-LATCH DATAPATHS; LOW-POWER DESIGN; MULTIPLE MODES; POWER GATING;

BENCHMARKING; CIRCUIT SIMULATION; COMBINATORIAL CIRCUITS; ENERGY CONSERVATION; FLIP FLOP CIRCUITS; POWER CONTROL;

LEAKAGE CURRENTS;

EID: 35448998108     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.904101     Document Type: Article

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