Improved timing closure by early buffer planning in floor-placement design flow

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 558-563

  Jahanian, Ali ^a   Zamani, Morteza Saheb ^b  

^a ISLAMIC AZAD UNIVERSITY   (Iran)

^b AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Buffer insertion; Buffer planning; Design convergence

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; CRITICAL PATH ANALYSIS; ELECTRIC POWER UTILIZATION; PROGRAM PROCESSORS; STATISTICAL METHODS;

BUFFER INSERTION; BUFFER PLANNING; DEEP SUBMICRON TECHNOLOGIES; DESIGN CONVERGENCE; FLOORPLANNING;

INTEGRATED CIRCUIT LAYOUT;

EID: 34748848275     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228916     Document Type: Conference Paper

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