Integrating buffer planning with floorplanning for simultaneous multi-objective optimization

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 624-627

  Cheng, Yi Hui ^a   Chang, Yao Wen ^b  

^a SYNOPSYS INC   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CONGESTION CONTROL (COMMUNICATION); ITERATIVE METHODS; LAGRANGE MULTIPLIERS; MATHEMATICAL MODELS; OBJECT ORIENTED PROGRAMMING; SIGNAL PROCESSING; SIMULATED ANNEALING; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

BUFFER INSERTION; BUFFER PLANNING; FLOOR PLANNING; TIMING OPTIMIZATION;

ELECTRIC NETWORK ANALYSIS;

EID: 2442576888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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