Provably good global buffering using an available buffer block plan

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 104-109

  Dragan, Feodor E ^a   Kahng, Andrew B ^a   Məndoiu, Ion ^b   Muddu, Sudhakar ^c   Zelikovsky, Alexander ^d  

^a University of California   (United States)

^b Georgia Institute of Technology   (United States)

^c HEWLETT PACKARD ENTERPRISE   (United States)

^d GEORGIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC INVERTERS; BUFFER STORAGE; CONSTRAINT THEORY; DATA HANDLING; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS;

BLOCK BASED; BUFFER BLOCK PLANNING; GLOBAL INTERCONNECTS; HIGH-END MICROPROCESSORS; PARITY CONSTRAINT; PIN CONNECTIONS; UPPER AND LOWER BOUNDS; WIRE LENGTH;

COMPUTER AIDED DESIGN;

BUFFER BLOCK PLAN; BUFFER PARITY CONSTRAINTS; GLOBAL BUFFERING; GLOBAL INTERCONNECT;

EID: 0034481509     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896458     Document Type: Conference Paper

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