Buffer planning as ah integral part of floorplanning with consideration of routing congestion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 4, 2005, Pages 609-620

  Ma, Yuchun ^a   Hong, Xianlong ^a   Donag, Sheqin ^a   Chen, Song ^a   Cheng, C K ^b   Gu, Jun ^c  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Buffer insertion; Computer aided design; Floorplanning; Routability; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTER AIDED DESIGN; CONGESTION CONTROL (COMMUNICATION); COSTS; OPTIMIZATION; ROUTERS; VLSI CIRCUITS;

BUFFER INSERTION; FLOORPLANNING; ROUTABILITY; ROUTING CONGESTION;

FLOORS;

EID: 16444378185     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.844103     Document Type: Article

References (17)

1. J. Cong. Challenges and opportunities for design innovations in nanometer technologies, presented at SRC Working Papers. [Online] Available: http://www.src.org1pr8mgmt/frontier.dgw
2. J. Cong, T. Kong, and D. Z. Pan, "Buffer block planning for interconnectdriven floorplanning," in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 358-363.
3. P. Sarkar, V. Sundararaman, and C.-K. Koh, "Routability-driven repeater block planning for interconnect-centric floorplanning," in Proc. Int. Symp. Physical Design, Apr. 2000, pp. 186-191.
4. X. P. Tang and D. Wong, "Planning buffer locations by network flows," in Proc. Int. Symp. Phys. Design, 2000, pp. 180-185.
5. C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. G. Villarrubia, "A practical methodology for early buffer and wire resource allocation," in Proc. Design Automation Conf., 2001, pp. 189-194.
6. X. Hong et al., "Corner block list: An effective and efficient topological representation of nonslicing floorplan," in Proc. ICCAD, 2000, pp. 8-12.
7. J. Cong, L. He, K.-Y. Khoo, C.-K. Koh, and Z. Pan, "Interconnect design for deep submicron ICs," in Proc. Int. Conf. Computer-Aided Design, Nov. 1997, pp. 478-485.
8. W. C. Elmore, "The transient response of damped linear networks with particular regard to wide-band amplifiers," J. Appl. Phys., vol. 19, no. 1, pp. 55-63, 1948.
9. J. Cong and D. Z. Pan, "Interconnect delay estimation models for synthesis and design planning," in Proc. Asia South Pacific Design Automation Conf., Jan. 1999, pp. 97-100.
10. Semiconductor Industry Association, National Technology Roadmap for Semiconductors San Jose, CA, 1997.
11. C. W. Sham and F. Y. Young, "Routibility driven floorplanner with buffer block planning," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 22, no. 4, pp. 470-480, Apr. 2003.
12. F. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu, and A. Zelikovsky, "Provably good global buffering using an available buffer block plan," in Proc. IEEE Int. Conf. Computer- Aided Design, 2000, pp. 104-109.
13. J. Lou, S. Krishnamoorthy, and H. S. Sheng, "Estimating routing congestion using probablistic analysis," in Proc. Int. Symp. Phys. Design, 2001, pp. 112-117.
14. C. Albrecht, A. B. Kahng, I. Mandoiu, and A. Zelikovsky, "Floorplan evaluation with timing-driven global wireplanning, pin assignment, and buffer/wire sizing," in Proc. Int. Conf. VLSI Design/ASPDAC, Jan. 2002, pp. 580-587.
15. S. Nahar and S. Sahni, "A fast algorithm for polygon decomposition," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 7, no. 4, pp. 478-483, Apr. 1988.
16. M. A. Lopez and D. P. Mehta, "Efficient decomposition of polygons into L-shapes with applications to VLSI layouts," ACM Trans. Design Automation Electron. Syst., vol. 1, no. 1, pp. 371-395, 1996.
17. J. Cong and Z. Pan, "Interconnect performance estimation models for design planning," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 20, no. 6, pp. 739-752, Jun. 2001.