Multi-level buffer block planning and buffer insertion for large design circuits

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

Volumn 2006, Issue , 2006, Pages 411-415

  Jahanian, Ali ^a   Zamani, Morteza Saheb ^a  

^a AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Buffer insertion; Buffer planning; Incremental placement

Indexed keywords

BUFFER CIRCUITS; CONGESTION CONTROL (COMMUNICATION); INSERTION LOSSES; ROUTERS; SIGNAL THEORY;

BUFFER BLOCK PLANNING; BUFFER INSERTION; INCREMENTAL PLACEMENTS;

INTEGRATED CIRCUIT LAYOUT;

EID: 33749339611     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2006.63     Document Type: Conference Paper

References (13)

1. D. Hill, and A. B. Kahng, "RTL to GDSII-From foilware to standard practice," IEEE Design & Test of Computers, 2004.
2. Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai, C.K.Cheng, and J. Gu,"An integrated floorplanning with an efficient buffer planning algorithm", IS PD, pp. 136-142, 2003.
3. L. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay", ISCAS, pp. 865-868, 1990.
4. C. J. Alpert, et. al., "Buffered steiner trees for difficult instances", ISPD, pp. 4-9, 2001.
5. M. Lai, and D. F. Wong, "Maze routing with buffer insertion and wiresizing", DAC, pp. 374-378, 2000.
6. V. Khandelwal, A. Davoodi, A. Nanavati, and A. Srivastava, "A probabilistic approach to buffer insertion", ICCAD, pp. 560-567, 2003.
7. J. Cong, T. Kong, and D. Z. Pan," Buffer block planning for interconnect-driven floorplanning", ICCAD, pp. 358-363, 1999.
8. P. Sarkar and C. K. Koh, "Routability-driven repeater block planning for interconnect-centric floorplanning", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 20, pp. 660-671, 2001.
9. K. W.C. Wong, and E. F.Y. Young, "Fast buffer planning and congestion optimization in interconnect-driven floorplanning", ASP-DAC, 2003.
10. G. Karypis and V. Kumar, "Parallel multilevel k-way partitioning scheme for irregular graphs", SIAM Rev., Vol.41, No.1,pp. 278-300, 1999.
11. D. Stroobandt, "A priori system-level interconnect prediction: Rent's rule and wire length distribution models", SLIP, pp. 3-21, 2001.
12. M. Wang, X. Ynag, and M. Sarrafzadeh, "DRAGON2000: standard-cell placement tool for large industry circuits", ICCAD, pp. 260-263, 2000.
13. W. Choi, and K. Bazargan, "Incremental placement for timing optimization", ICCAD, pp. 463-466, 2003.