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Volumn , Issue , 2006, Pages 103-112

A methodology for abstracting RTL designs into TL descriptions

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; COMPUTATIONAL COMPLEXITY; VERIFICATION;

EID: 34548828182     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (17)
  • 1
    • 40949105788 scopus 로고    scopus 로고
    • J. Krasner. Embedded Software Development Issues and Challenges. Embedded Market Forecaster, 2003.
    • J. Krasner. Embedded Software Development Issues and Challenges. Embedded Market Forecaster, 2003.
  • 3
    • 40949115228 scopus 로고    scopus 로고
    • Advancing Transaction Level Modeling: Linking the OSCI and OCP-IP Worlds at Transaction Level
    • J. Colgan and P. Hardee. Advancing Transaction Level Modeling: Linking the OSCI and OCP-IP Worlds at Transaction Level. White paper.
    • White paper
    • Colgan, J.1    Hardee, P.2
  • 8
    • 33644988200 scopus 로고    scopus 로고
    • Design for Verification of SystemC Transaction Level Models
    • A. Habibi and S. Tahar. Design for Verification of SystemC Transaction Level Models. In IEEE DATE, pp. 560-565. 2005.
    • (2005) IEEE DATE , pp. 560-565
    • Habibi, A.1    Tahar, S.2
  • 9
    • 34547757490 scopus 로고    scopus 로고
    • On PSL Properties Re-use in SoC Design Flow Based on Transactional Level Modeling
    • N. Bombieri, A. Fedeli, and F. Fummi. On PSL Properties Re-use in SoC Design Flow Based on Transactional Level Modeling. In IEEE MTV. 2005.
    • (2005) IEEE MTV
    • Bombieri, N.1    Fedeli, A.2    Fummi, F.3
  • 10
    • 84943596560 scopus 로고    scopus 로고
    • Verification of Transaction-Level SystemC Models Using RTL Testbenches
    • R. Jindal and K. Jain. Verification of Transaction-Level SystemC Models Using RTL Testbenches. In ACM/IEEE MEMOCODE, pp. 199-203. 2003.
    • (2003) ACM/IEEE MEMOCODE , pp. 199-203
    • Jindal, R.1    Jain, K.2
  • 11
    • 34047134555 scopus 로고    scopus 로고
    • Functional Verification Methodology based on Formal Interface Specification and Transactor Generation
    • F. Balarin and R. Passerone. Functional Verification Methodology based on Formal Interface Specification and Transactor Generation. In Proc. of IEEE DATE. 2006.
    • (2006) Proc. of IEEE DATE
    • Balarin, F.1    Passerone, R.2
  • 12
    • 34047111321 scopus 로고    scopus 로고
    • On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL
    • N. Bombieri, F. Fummi, and G. Pravadelli. On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL. In Proc. of IEEE DATE. 2006.
    • (2006) Proc. of IEEE DATE
    • Bombieri, N.1    Fummi, F.2    Pravadelli, G.3
  • 13
    • 0002063138 scopus 로고    scopus 로고
    • Automatic Generation of Functional Vectors Using the Extended Finite State Machine Model
    • K. Cheng and A. Krishnakumar. Automatic Generation of Functional Vectors Using the Extended Finite State Machine Model. ACM Trans. on Design Automation of Electronic Systems, vol. 1(1):pp. 57-79, 1996.
    • (1996) ACM Trans. on Design Automation of Electronic Systems , vol.1 , Issue.1 , pp. 57-79
    • Cheng, K.1    Krishnakumar, A.2
  • 15
    • 4243696949 scopus 로고    scopus 로고
    • Essential Issue in Codesign
    • University of California, Irvine
    • D. Gajski, J. Zhu, and R. Domer. Essential Issue in Codesign. Thecnical report ICS-97-26, University of California, Irvine, 1997.
    • (1997) Thecnical report ICS-97-26
    • Gajski, D.1    Zhu, J.2    Domer, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.