On PSL properties re-use in SoC design flow based on transaction level modeling

Proceedings - International Workshop on Microprocessor Test and Verification

Volumn , Issue , 2005, Pages 127-132

  Bombieri, Nicola ^a   Fedeli, Andrea ^a   Fummi, Franco ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF VERONA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; MICROPROCESSOR CHIPS; VERIFICATION;

SYSTEM DEVELOPMENT; SYSTEM ON CHIP (SOC) DESIGNS; TRANSACTION LEVEL MODELING (TLM);

SPECIFICATION LANGUAGES;

EID: 34547757490     PISSN: 15504093     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTV.2005.15     Document Type: Conference Paper

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