Two efficient synchronous {A figure is presented} asynchronous converters well-suited for networks-on-chip in GALS architectures

Integration, the VLSI Journal

Volumn 41, Issue 1, 2008, Pages 17-26

  Sheibanyrad, A ^a   Greiner, A ^a  

^a SORBONNE UNIVERSITÉ   (France)

Author keywords

Asynchronous FIFO; Globally asynchronous locally synchronous; Multi processor systems on chip; Networks on chip; Synchronization

Indexed keywords

ASYNCHRONOUS MACHINERY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL LIBRARIES; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; ROBUSTNESS (CONTROL SYSTEMS); SPICE;

ASYNCHRONOUS FIFO; MULTI-PROCESSOR SYSTEMS-ON-CHIP; NETWORKS-ON-CHIP;

ANALOG TO DIGITAL CONVERSION;

EID: 34548481505     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2007.04.006     Document Type: Article

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